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Unformatted text preview: erved Task Priority Register Arbitration Priority Register Processor Priority Register EOI Register Reserved Logical Destination Register Destination Format Register Spurious-Interrupt Vector Register ISR 0-255 TMR 0-255 IRR 0-255 Error Status Register Reserved Interrupt Command Reg. 0-31 Interrupt Command Reg. 32-63 Local Vector Table (Timer) Reserved Performance Counter LVT1 Local Vector Table (LINT0) Local Vector Table (LINT1) Local Vector Table (Error)2 Initial Count Register for Timer Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Bits 0-27 Read only. Bits 28-31 Read/Write Bits 0-3 Read only. Bits 4-9 Read/Write Read only Read only Read only Read only Read/Write Read only Read only Write only Read/write Read only Register Name Software Read/Write MULTIPLE-PROCESSOR MANAGEMENT Table 7-1. Local APIC Register Address Map (Contd.)
Address FEE0 0390H FEE0 03A0H through FEE0 03D0H FEE0 03E0H FEE0 03F0H NOTES: 1. Introduced into the APIC Architecture in the Pentium® Pro processor. 2. Introduced into the APIC Architecture in the Pentium® processor. Register Name Current Count Register for Timer Reserved Timer Divide Configuration Register Reserved Read/Write Software Read/Write Read only 7.5.8. Relocation of the APIC Registers Base Address The P6 family processors permit the starting address of the APIC registers to be relocated from FEE00000H to another physical address. This extension of the APIC architecture is provided to help resolve conflicts with memory maps of existing systems. The P6 family processors also provide the ability to enable or disable the local APIC. An alternate APIC base address is specified through the APIC_BASE_MSR register. This MSR is located at MSR address 27 (1BH). Figure 7-4 shows the encoding of the bits in this register. This register also provides the flag for enabling or disabling the local APIC. The functions of the bits in the APIC_BASE_MSR register are as follows: BSP flag, bit 8 Indicates if the processor is the bootstrap processor (BSP), determined during the MP initialization (refer to Section 7.7., “Multiple-Processor (MP) Initialization Protocol”). Following a power-up or reset, this flag is clear for all the processors in the system except the single BSP. 63 36 35 12 11 10 9 8 7 0 Reserved APIC Base—Base physical address E—APIC enable/disable BSP—Processor is BSP Reserved APIC Base Figure 7-4. APIC_BASE_MSR E (APIC Enabled) flag, bit 11 Permits the local APIC to be enabled (set) or disabled (clear). Following a power-up or reset, this flag is set, enabling the local APIC. When this flag is 7-19 MULTIPLE-PROCESSOR MANAGEMENT clear, the processor is functionally equivalent to an Intel Architecture processor without an on-chip APIC (for example, an Intel486™ processor). This flag is implementation dependent and in not guaranteed to be available or available at the same location in future Intel Architecture processors. APIC Base field, bits 12 through 35 Specifies the base address of the APIC registers. This 24-bit value is extended by 12 bits at the low end to form the base address, which automatically aligns the address on a 4-KByte boundary. Following a power-up or reset, this field is set to FEE00000H. Bits 0 through 7, bits 9 and 10, and bits 36 through 63 in the APIC_BASE_MSR register are reserved. 7.5.9. Interrupt Destination and APIC ID The destination of an interrupt can be one, all, or a subset of the processors in the system. The sender specifies the destination of an interrupt in one of two destination modes: physical or logical. 184.108.40.206. PHYSICAL DESTINATION MODE In physical destination mode, the destination processor is specified by its local APIC ID. This ID is matched against the local APIC’s actual physical ID, which is stored in the local APIC ID register (refer to Figure 7-5). Either a single destination (the ID is 0 through 14) or a broadcast to all (the ID is 15) can be specified in physical destination mode. Note that in this mode, up to 15 the local APICs can be individually addressed. An ID of all 1s denotes a broadcast to all local APICs. The APIC ID register is loaded at power up by sampling configuration data that is driven onto pins of the processor. For the P6 family processors, pins A11# and A12# and pins BR0# through BR3# are sampled; for the Pentium® processor, pins BE0# through BE3# are sampled. The ID portion can be read and modified by software.
31 28 27 24 23 0 Reserved APIC ID Reserved Address: 0FEE0 0020H Value after reset: 0000 0000H Figure 7-5. Local APIC ID Register 220.127.116.11. LOGICAL DESTINATION MODE In logical destination mode, message destinations are specified using an 8-bit message destination address (MDA). The MDA is compared against the 8-bit logical APIC ID field of the APIC logical destination register (LDR), refer to Figure 7-6. 7-20 MULTIPLE-PROCESSOR MANAGEMENT 31 24 23 0 Logical APIC ID Address: 0FEE0 00D0H Value after reset: 0000 0000H Reserved Figure 7-6. Logical Destination Register (LDR) Destina...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10