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75162 apic bus status cycles certain cycles within an

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Unformatted text preview: 20 7-38 MULTIPLE-PROCESSOR MANAGEMENT are same as for the short message. If during the status cycle (cycle 19) the state of the (A:A) flags is 10B, a focus processor has been identified, and the short message format is used (refer to Table 7-4). If the (A:A) flags are set to 00B, lowest priority arbitration is started and the 34cycles of the nonfocused lowest priority message are competed. For other combinations of status flags, refer to Section 7.5.16.2., “APIC Bus Status Cycles” Table 7-5. Nonfocused Lowest Priority Message (34 Cycles) Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 Cycle 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Bit0 0 ArbID3 ArbID2 ArbID1 ArbID0 DM M1 L V7 V5 V3 V1 D7 Bit0 D5 D3 D1 C 0 A A1 P7 P6 P5 P4 P3 P2 P1 P0 ArbID3 ArbID2 ArbID1 ArbID0 A2 0 Bit1 1 0 0 0 0 M2 M0 TM V6 V4 V2 V0 D6 Bit1 D4 D2 D0 C 0 A A1 0 0 0 0 0 0 0 0 0 0 0 0 A2 0 Status Cycle Idle 7-39 Arbitration ID 3 -0 Status cycle 0 Status cycle 1 P7 - P0 = Inverted Processor Priority Checksum for cycles 6-16 D7-D0 = Destination DM = Destination mode M2-M0 = Delivery mode L = Level, TM = Trigger Mode V7-V0 = Interrupt Vector 0 1 = normal Arbitration ID bits 3 through 0 MULTIPLE-PROCESSOR MANAGEMENT Cycles 21 through 28 are used to arbitrate for the lowest priority processor. The processors participating in the arbitration drive their inverted processor priority on the bus. Only the local APICs having free interrupt slots participate in the lowest priority arbitration. If no such APIC exists, the message will be rejected, requiring it to be tried at a later time. Cycles 29 through 32 are also used for arbitration in case two or more processors have the same lowest priority. In the lowest priority delivery mode, all combinations of errors in cycle 33 (A2 A2) will set the “accept error” bit in the error status register (refer to Figure 7-16). Arbitration priority update is performed in cycle 20, and is not affected by errors detected in cycle 33. Only the local APIC that wins in the lowest priority arbitration, drives cycle 33. An error in cycle 33 will force the sender to resend the message. 7.5.16.2. APIC BUS STATUS CYCLES Certain cycles within an APIC bus message are status cycles. During these cycles the status flags (A:A) and (A1:A1) are examined. Table 7-6 shows how these status flags are interpreted, depending on the current delivery mode and existence of a focus processor. Table 7-6. APIC Bus Status Cycles Interpretation Delivery Mode EOI Update ArbID and Cycle# Yes, 13 Yes, 13 No No No No Yes, 20 Yes, 20 No No No No Yes, 20 Yes, 20 No No No No Message Length 14 Cycle 14 Cycle 14 Cycle 14 Cycle 14 Cycle 14 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle 21 Cycle A Status 00: CS_OK 00: CS_OK 00: CS_OK 11: CS_Error 10: Error 01: Error A1 Status 10: Accept 11: Retry 0X: Accept Error XX: XX: XX: 10: Accept 11: Retry 0X: Accept Error XX: XX: XX: 10: Accept 11: Retry 0X: Accept Error XX: XX: XX: A2 Status XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: XX: Retry No Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Fixed 00: CS_OK 00: CS_OK 00: CS_OK 11: CS_Error 10: Error 01: Error NMI, SMI, INIT, ExtINT, Start-Up 00: CS_OK 00: CS_OK 00: CS_OK 11: CS_Error 10: Error 01: Error 7-40 MULTIPLE-PROCESSOR MANAGEMENT Table 7-6. APIC Bus Status Cycles Interpretation (Contd.) Lowest 00: CS_OK, NoFocus 00: CS_OK, NoFocus 00: CS_OK, NoFocus 00: CS_OK, NoFocus 00: CS_OK, NoFocus 10: CS_OK, Focus 11: CS_Error 01: Error 11: Do Lowest 11: Do Lowest 11: Do Lowest 10: End and Retry 0X: Error XX: XX: XX: 10: Accept 11: Error 0X: Error XX: XX: XX: XX: XX: Yes, 20 Yes, 20 Yes, 20 Yes, 20 No Yes, 20 No No 34 Cycle 34 Cycle 34 Cycle 34 Cycle 34 Cycle 34 Cycle 21 Cycle 21 Cycle No Yes Yes Yes Yes No Yes Yes 7-41 MULTIPLE-PROCESSOR MANAGEMENT 7.5.17. Error Handling The local APIC sets flags in the error status register (ESR) to record all the errors that is detects (refer to Figure 7-16). The ESR is a read/write register and is reset after being written to by the processor. A write to the ESR must be done just prior to reading the ESR to allow the register to be updated. An error interrupt is generated when one of the error bits is set. Error bits are cumulative. The ESR must be cleared by software after unmasking of the error interrupt entry in the LVT is performed (by executing back-to-back a writes). If the software, however, wishes to handle errors set in the register prior to unmasking, it should write and then read the ESR prior or immediately after the unmasking. 31 876 54 32 1 0 Reserved Illegal Register Address Received Illegal Vector Send Illegal Vector Reserved Receive Accept Error Send Accept Error Receive CS Error Send CS Error Address: FEE0 0280H Value after reset: 0H Figure 7-16. Error Status Register (ESR) 7-42 MULTIPLE-PROCESSOR MANAGEMENT The functions of the ESR flags are as follows: Send CS Error Receive CS Error Send Accept Error Receive Accept Error Send Illegal Vector Receive Illegal Vector Set when the...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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