IntelSoftwareDevelopersManual

91 assembler usage in this example the intel

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Unformatted text preview: pt is not disabled following a reset. The NMI# pin must thus be inhibited from being asserted until an NMI handler has been loaded and made available to the processor. The use of a temporary GDT allows simple transfer of tables from the EPROM to anywhere in the RAM area. A GDT entry is constructed with its base pointing to address 0 and a limit of 4 GBytes. When the DS and ES registers are loaded with this descriptor, the temporary GDT is no longer needed and can be replaced by the application GDT. This code loads one TSS and no LDTs. If more TSSs exist in the application, they must be loaded into RAM. If there are LDTs they may be loaded as well. After Reset [CS.BASE+EIP] FFFF FFFFH FFFF FFF0H • • • 64K EPROM EIP = 0000 FFF0H CS.BASE = FFFF 0000H DS.BASE = 0H ES.BASE = 0H SS.BASE = 0H ESP = 0H FFFF 0000H [SP, DS, SS, ES] 0 Figure 8-3. Processor State After Reset 8-17 PROCESSOR MANAGEMENT AND INITIALIZATION Table 8-4. Main Initialization Steps in STARTUP.ASM Source Listing STARTUP.ASM Line Numbers From 157 162 157 169 To Description Jump (short) to the entry code in the EPROM Construct a temporary GDT in RAM with one entry: 0 - null 1 - R/W data segment, base = 0, limit = 4 GBytes Load the GDTR to point to the temporary GDT Load CR0 with PE flag set to switch to protected mode Jump near to clear real mode instruction queue Load DS, ES registers with GDT[1] descriptor, so both point to the entire physical memory space Perform specific board initialization that is imposed by the new protected mode Copy the application’s GDT from ROM into RAM Copy the application’s IDT from ROM into RAM Load application’s GDTR Load application’s IDTR Copy the application’s TSS from ROM into RAM Update TSS descriptor and other aliases in GDT (GDT alias or IDT alias) Load the task register (without task switch) using LTR instruction Load SS, ESP with the value found in the application’s TSS Push EFLAGS value found in the application’s TSS Push CS value found in the application’s TSS Push EIP value found in the application’s TSS Load DS, ES with the value found in the application’s TSS Perform IRET; pop the above values and enter the application code 171 174 179 184 188 196 220 241 244 247 263 277 282 287 288 289 290 296 172 177 181 186 195 218 238 243 245 261 267 277 286 287 288 289 293 296 8-18 PROCESSOR MANAGEMENT AND INITIALIZATION 8.9.1. Assembler Usage In this example, the Intel assembler ASM386 and build tools BLD386 are used to assemble and build the initialization code module. The following assumptions are used when using the Intel ASM386 and BLD386 tools. • • The ASM386 will generate the right operand size opcodes according to the code-segment attribute. The attribute is assigned either by the ASM386 invocation controls or in the code-segment definition. If a code segment that is going to run in real-address mode is defined, it must be set to a USE 16 attribute. If a 32-bit operand is used in an instruction in this code segment (for example, MOV EAX, EBX), the assembler automatically generates an operand prefix for the instruction that forces the processor to execute a 32-bit operation, even though its default code-segment attribute is 16-bit. Intel’s ASM386 assembler allows specific use of the 16- or 32-bit instructions, for example, LGDTW, LGDTD, IRETD. If the generic instruction LGDT is used, the defaultsegment attribute will be used to generate the right opcode. • 8.9.2. STARTUP.ASM Listing The source code listing to move the processor into protected mode is provided in Example 8-1. This listing does not include any opcode and offset information. Example 8-1. STARTUP.ASM MS-DOS* 5.0(045-N) 386(TM) MACRO ASSEMBLER STARTUP 09:44:51 08/19/92 PAGE 1 MS-DOS 5.0(045-N) 386(TM) MACRO ASSEMBLER V4.0, ASSEMBLY OF MODULE STARTUP OBJECT MODULE PLACED IN startup.obj ASSEMBLER INVOKED BY: f:\386tools\ASM386.EXE startup.a58 pw (132 ) LINE 1 2 3 SOURCE NAME STARTUP ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 4; 5 ; ASSUMPTIONS: 6; 7 ; 1. The bottom 64K of memory is ram, and can be used for 8; scratch space by this module. 9; 10 ; 2. The system has sufficient free usable ram to copy the 11 ; initial GDT, IDT, and TSS 8-19 PROCESSOR MANAGEMENT AND INITIALIZATION 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; configuration data - must match with build definition CS_BASE EQU 0FFFF0000H ; CS_BASE is the linear address of the segment STARTUP_CODE ; - this is specified in the build language file RAM_START EQU 400H ; RAM_START is the start of free, usable ram in the linear ; memory space. The GDT, IDT, and initial TSS will be ; copied above this space, and a small data segment will be ; discarded at this linear address. The 32-bit word at ; RAM_START will contain the linear address of the first ; free byte above the copied tables - this may be useful if ; a memory manager is used. TSS_INDEX EQU 10 ; TSS_INDEX is the index of the TSS of the first task to ; run after startup ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ------------------------- STRUCTURES and EQU --------------; structures for system data ; TSS structure TASK_STATE STRUC link DW ? link_h DW ? ESP0 DD ? SS0 DW ? SS0_h DW ? ESP1 DD ? SS1 DW ? SS1_h DW ? ESP2 DD ? SS2 DW ? SS2_h DW ? CR3_reg DD ? EIP_reg DD ? EFLAGS_reg DD...
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