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A 14 performance monitoring events table a 2 events

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Unformatted text preview: EBL) events, except where noted, can be further qualified using the Unit Mask (UMSK) field in the PerfEvtSel0 and PerfEvtSel1 registers. Bit 5 of the UMSK field is used in conjunction with the EBL events to indicate whether the processor should count transactions that are selfgenerated (UMSK[5] = 0) or transactions that result from any processor on the bus (UMSK[5] = 1). 3. L2 cache locks, so it is possible to have a zero count. A-11 PERFORMANCE-MONITORING EVENTS A.2. PENTIUM® PROCESSOR PERFORMANCE-MONITORING EVENTS Table A-2 lists the events that can be counted with the performance-monitoring counters for the Pentium® processor. The Event Number column gives the hexadecimal code that identifies the event and that is entered in the ES0 or ES1 (event select) fields of the CESR MSR. The Mnemonic Event Name column gives the name of the event, and the Description and Comments columns give detailed descriptions of the events. Most events can be counted with either counter 0 or counter 1; however, some events can only be counted with only counter 0 or only counter 1 (as noted). NOTE The events in the table that are shaded are implemented only in the Pentium® processor with MMX™ technology. Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters Event Num. 00H Mnemonic Event Name DATA_READ Description Number of memory data reads (internal data cache hit and miss combined). Comments Split cycle reads are counted individually. Data Memory Reads that are part of TLB miss processing are not included. These events may occur at a maximum of two per clock. I/O is not included. Split cycle writes are counted individually. These events may occur at a maximum of two per clock. I/O is not included. 01H DATA_WRITE Number of memory data writes (internal data cache hit and miss combined), I/O is not included. Number of misses to the data cache translation look-aside buffer. Number of memory read accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. 0H2 DATA_TLB_MISS 03H DATA_READ_MISS Additional reads to the same cache line after the first BRDY# of the burst line fill is returned but before the final (fourth) BRDY# has been returned, will not cause the counter to be incremented additional times. Data accesses that are part of TLB miss processing are not included. Accesses directed to I/O space are not included. Data accesses that are part of TLB miss processing are not included. Accesses directed to I/O space are not included. 04H DATA WRITE MISS Number of memory write accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. A-12 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.) Event Num. 05H Mnemonic Event Name WRITE_HIT_TO_ M-_OR_ESTATE_LINES DATA_CACHE_ LINES_ WRITTEN_BACK EXTERNAL_ SNOOPS Description Number of write hits to exclusive or modified lines in the data cache. Number of dirty lines (all) that are written back, regardless of the cause. Number of accepted external snoops whether they hit in the code cache or data cache or neither. Number of external snoops to the data cache. Comments These are the writes that may be held up if EWBE# is inactive. These events may occur a maximum of two per clock. Replacements and internal and external snoops can all cause writeback and are counted. Assertions of EADS# outside of the sampling interval are not counted, and no internal snoops are counted. Snoop hits to a valid line in either the data cache, the data line fill buffer, or one of the write back buffers are all counted as hits. These accesses are not necessarily run in parallel due to cache misses, bank conflicts, etc. 06H 07H 08H EXTERNAL_DATA_ CACHE_SNOOP_ HITS MEMORY ACCESSES IN BOTH PIPES BANK CONFLICTS MISALIGNED DATA MEMORY OR I/O REFERENCES 09H Number of data memory reads or writes that are paired in both pipes of the pipeline. Number of actual bank conflicts. Number of memory or I/O reads or writes that are misaligned. 0AH 0BH A 2- or 4-byte access is misaligned when it crosses a 4-byte boundary; an 8-byte access is misaligned when it crosses an 8-byte boundary. Ten byte accesses are treated as two separate accesses of 8 and 2 bytes each. Individual 8-byte noncacheable instruction reads are counted. 0CH CODE READ Number of instruction reads whether the read is cacheable or noncacheable. Number of instruction reads that miss the code TLB whether the read is cacheable or noncacheable. Number of instruction reads that miss the internal code cache whether the read is cacheable or noncacheable. 0DH CODE TLB MISS Individual 8-byte noncacheable instruction reads are counted. 0EH CODE CACHE MISS Individual 8-byte noncacheable instruction reads are counted. A-13 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.) Event Num. 0FH Mnemonic Event...
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