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Unformatted text preview: Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.)
Event Num. 2EH Mnemonic Event Name WRITES_TO_ NONCACHEABLE_ MEMORY (Counter 1) SATURATING_ MMX_ INSTRUCTIONS_ EXECUTED (Counter 0) SATURATIONS_ PERFORMED (Counter 1) Description Number of write accesses to noncacheable memory. Comments The count includes write cycles caused by TLB misses and I/O write cycles. Cycles restarted due to BOFF# are not re-counted. 2FH Number of saturating MMX™ instructions executed, independently of whether they actually saturated. Number of MMX™ instructions that used saturating arithmetic and that at least one of its results actually saturated. Number of cycles the processor is not idle due to HLT instruction. If an MMX™ instruction operating on 4 doublewords saturated in three out of the four results, the counter will be incremented by one only. This event will enable the user to calculate “net CPI”. Note that during the time that the processor is executing the HLT instruction, the Time-Stamp Counter is not disabled. Since this event is controlled by the Counter Controls CC0, CC1 it can be used to calculate the CPI at CPL=3, which the TSC cannot provide. 2FH 30H NUMBER_OF_ CYCLES_NOT_IN_ HALT_STATE (Counter 0) 30H DATA_CACHE_ TLB_MISS_ STALL_DURATION (Counter 1) MMX_ INSTRUCTION_ DATA_READS (Counter 0) MMX_ INSTRUCTION_ DATA_READ_ MISSES (Counter 1) FLOATING_POINT_ STALLS_DURATION (Counter 0) TAKEN_BRANCHES (Counter 1) D1_STARVATION_ AND_FIFO_IS_ EMPTY (Counter 0) Number of clocks the pipeline is stalled due to a data cache translation look-aside buffer (TLB) miss. Number of MMX™ instruction data reads. 31H 31H Number of MMX™ instruction data read misses. 32H Number of clocks while pipe is stalled due to a floating-point freeze. Number of taken branches. Number of times D1 stage cannot issue ANY instructions since the FIFO buffer is empty. The D1 stage can issue 0, 1, or 2 instructions per clock if those are available in an instructions FIFO buffer. 32H 33H A-19 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.)
Event Num. 33H Mnemonic Event Name D1_STARVATION_ AND_ONLY_ONE_ INSTRUCTION_IN_ FIFO (Counter 1) Description Number of times the D1 stage issues just a single instruction since the FIFO buffer had just one instruction ready. Comments The D1 stage can issue 0, 1, or 2 instructions per clock if those are available in an instructions FIFO buffer. When combined with the previously defined events, Instruction Executed (16H) and Instruction Executed in the Vpipe (17H), this event enables the user to calculate the numbers of time pairing rules prevented issuing of two instructions. 34H MMX_ INSTRUCTION_ DATA_WRITES (Counter 0) MMX_ INSTRUCTION_ DATA_WRITE_ MISSES (Counter 1) PIPELINE_ FLUSHES_DUE_ TO_WRONG_ BRANCH_ PREDICTIONS (Counter 0) Number of data writes caused by MMX™ instructions. Number of data write misses caused by MMX™ instructions. 34H 35H Number of pipeline flushes due to wrong branch predictions resolved in either the Estage or the WB-stage. The count includes any pipeline flush due to a branch that the pipeline did not follow correctly. It includes cases where a branch was not in the BTB, cases where a branch was in the BTB but was mispredicted, and cases where a branch was correctly predicted but to the wrong address. Branches are resolved in either the Execute stage (Estage) or the Writeback stage (WBstage). In the later case, the misprediction penalty is larger by one clock. The difference between the 35H event count in counter 0 and counter 1 is the number of E-stage resolved branches. Refer to note for event 35H (Counter 0). 35H PIPELINE_ FLUSHES_DUE_ TO_WRONG_ BRANCH_ PREDICTIONS_ RESOLVED_IN_ WB-STAGE (Counter 1) MISALIGNED_ DATA_MEMORY_ REFERENCE_ON_ MMX_ INSTRUCTIONS (Counter 0) Number of pipeline flushes due to wrong branch predictions resolved in the WB-stage. 36H Number of misaligned data memory references when executing MMX™ instructions. A-20 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.)
Event Num. 36H Mnemonic Event Name PIPELINE_ ISTALL_FOR_MMX_ INSTRUCTION_ DATA_MEMORY_ READS (Counter 1) MISPREDICTED_ OR_ UNPREDICTED_ RETURNS (Counter 1) PREDICTED_ RETURNS (Counter 1) MMX_MULTIPLY_ UNIT_INTERLOCK (Counter 0) Description Number clocks during pipeline stalls caused by waits form MMX™ instruction data memory reads. Number of returns predicted incorrectly or not predicted at all. The count is the difference between the total number of executed returns and the number of returns that were correctly predicted. Only RET instructions are counted (for example, IRET instructions are not counted). Only RET instructions are counted (for example, IRET instructions are not counted). The counter will not be incremented if there is another cause for a stall. For each occurrence of a multiply interlock this...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10