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Unformatted text preview: t or a read-only data segment. Reading from an execute-only code segment. Loading the SS register with a segment selector for a read-only segment (unless the selector comes from a TSS during a task switch, in which case an invalid-TSS exception occurs). Loading the SS, DS, ES, FS, or GS register with a segment selector for a system segment. Loading the DS, ES, FS, or GS register with a segment selector for an execute-only code segment. Loading the SS register with the segment selector of an executable segment or a null segment selector. Loading the CS register with a segment selector for a data segment or a null segment selector. Accessing memory using the DS, ES, FS, or GS register when it contains a null segment selector. Switching to a busy task during a call or jump to a TSS. Switching to an available (nonbusy) task during the execution of an IRET instruction. Using a segment selector on task switch that points to a TSS descriptor in the current LDT. TSS descriptors can only reside in the GDT. Violating any of the privilege rules described in Chapter 4, Protection. Exceeding the instruction length limit of 15 bytes (this only can occur when redundant prefixes are placed before an instruction). 5-41 INTERRUPT AND EXCEPTION HANDLING • • • • • • • • • • • • • • Loading the CR0 register with a set PG flag (paging enabled) and a clear PE flag (protection disabled). Loading the CR0 register with a set NW flag and a clear CD flag. Referencing an entry in the IDT (following an interrupt or exception) that is not an interrupt, trap, or task gate. Attempting to access an interrupt or exception handler through an interrupt or trap gate from virtual-8086 mode when the handler’s code segment DPL is greater than 0. Attempting to write a 1 into a reserved bit of CR4. Attempting to execute a privileged instruction when the CPL is not equal to 0 (refer to Section 4.9., “Privileged Instructions” in Chapter 4, Protection for a list of privileged instructions). Writing to a reserved bit in an MSR. Accessing a gate that contains a null segment selector. Executing the INT n instruction when the CPL is greater than the DPL of the referenced interrupt, trap, or task gate. The segment selector in a call, interrupt, or trap gate does not point to a code segment. The segment selector operand in the LLDT instruction is a local type (TI flag is set) or does not point to a segment descriptor of the LDT type. The segment selector operand in the LTR instruction is local or points to a TSS that is not available. The target code-segment selector for a call, jump, or return is null. If the PAE and/or PSE flag in control register CR4 is set and the processor detects any reserved bits in a page-directory-pointer-table entry set to 1. These bits are checked during a write to control registers CR0, CR3, or CR4 that causes a reloading of the pagedirectory-pointer-table entry. A program or task can be restarted following any general-protection exception. If the exception occurs while attempting to call an interrupt handler, the interrupted program can be restartable, but the interrupt may be lost. Exception Error Code The processor pushes an error code onto the exception handler’s stack. If the fault condition was detected while loading a segment descriptor, the error code contains a segment selector to or IDT vector number for the descriptor; otherwise, the error code is 0. The source of the selector in an error code may be any of the following: • • •
5-42 An operand of the instruction. A selector from a gate which is the operand of the instruction. A selector from a TSS involved in a task switch. INTERRUPT AND EXCEPTION HANDLING • IDT vector number. Saved Instruction Pointer The saved contents of CS and EIP registers point to the instruction that generated the exception. Program State Change In general, a program-state change does not accompany a general-protection exception, because the invalid instruction or operation is not executed. An exception handler can be designed to correct all of the conditions that cause general-protection exceptions and restart the program or task without any loss of program continuity. If a general-protection exception occurs during a task switch, it can occur before or after the commit-to-new-task point (refer to Section 6.3., “Task Switching” in Chapter 6, Task Management). If it occurs before the commit point, no program state change occurs. If it occurs after the commit point, the processor will load all the state information from the new TSS (without performing any additional limit, present, or type checks) before it generates the exception. The general-protection exception handler should thus not rely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, and GS registers without causing another exception. (Refer to the Program State Change description for “Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.) 5-43 INTERRUPT AND EXCEPTION HANDLING Interrupt 14—Page-Fault Exception (#PF)
Exception Class Description Indicates that, with paging enabled (the PG flag...
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