IntelSoftwareDevelopersManual

Because the exception flags are sticky they provide a

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Unformatted text preview: on conditions described above has corresponding flag and mask bits in the MXCSR. If an exception is masked (the corresponding mask bit in MXCSR = 1), the processor takes an appropriate default action and continues with the computation. If the exception is unmasked (mask bit = 0) and the OS supports SIMD floating-point exceptions (i.e. CR4.OSXMMEXCPT = 1), a software exception handler is invoked immediately through SIMD floating-point exception interrupt vector 19. If the exception is unmasked (mask bit = 0) and the OS does not support SIMD floating-point exceptions (i.e. CR4.OSXMMEXCPT = 0), an invalid opcode exception is signaled instead of a SIMD floating-point exception. Note that because SIMD floating-point exceptions are precise and occur immediately, the situation does not arise where an x87-FP instruction, an FWAIT instruction, or another Streaming SIMD Extensions instruction will catch a pending unmasked SIMD floating-point exception. 11.7.2.1. EXCEPTION PRIORITY The processor handles exceptions according to a predetermined precedence. When a suboperand of a packed instruction generates two or more exception conditions, the exception precedence sometimes results in the higher-priority exception being handled and the lowerpriority exceptions being ignored. For example, dividing an SNaN by zero could potentially signal an invalid-arithmetic-operand exception (due to the SNaN operand) and a divide-by-zero exception. Here, if both exceptions are masked, the processor handles the higher-priority exception only (the invalid-arithmetic-operand exception), returning the quiet version of the SNaN to 11-13 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING the destination. The prioritization policy also applies for unmasked exceptions; if both invalid and divide-by-zero are unmasked for the previous example, only the invalid flag will be set. Prioritization of exceptions is performed only on an individual sub-operand basis, and not between suboperands; for example, an invalid exception generated by one sub-operand will not prevent the reporting of a divide-by-zero exception generated by another sub-operand. The precedence for SIMD floating-point numeric exceptions is as follows: 1. Invalid operation exception due to NaN operands (refer to Table 11-8). 2. QNaN operand. Though this is not an exception, the handling of a QNaN operand has precedence over lower-priority exceptions. For example, a QNaN divided by zero results in a QNaN, not a zero-divide exception. 3. Any other invalid operation exception not mentioned above or a divide-by-zero exception (refer to Table 11-8). 4. Denormal operand exception. If masked, then instruction execution continues, and a lower-priority exception can occur as well. 5. Numeric overflow and underflow exceptions possibly in conjunction with the inexact result exception. 6. Inexact result exception. 11.7.2.2. AUTOMATIC MASKED EXCEPTION HANDLING If the processor detects an exception condition for a masked exception (an exception with its mask bit set), it delivers a predefined (default) response and continues executing instructions. The masked (default) responses to exceptions have been chosen to deliver a reasonable result for each exception condition and are generally satisfactory for most application code. By masking or unmasking specific floating-point exceptions in the MXCSR, programmers can delegate responsibility for most exceptions to the processor and reserve the most severe exception conditions for software exception handlers. Because the exception flags are “sticky,” they provide a cumulative record of the exceptions that have occurred since they were last cleared. A programmer can thus mask all exceptions, run a calculation, and then inspect the exception flags to see if any exceptions were detected during the calculation. Note that when exceptions are masked, the processor may detect multiple exceptions in a single instruction, because: • • • It continues executing the instruction after performing its masked response; for example, the processor could detect a denormalized operand, perform its masked response to this exception, and then detect an underflow Exceptions may occur naturally in pairs, such as numeric underflow and inexact result (precision) Packed instructions can produce independent exceptions for each pair of operands. 11-14 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING Updating of exception flags is generated by a logical-OR of exception conditions for all suboperand computations, where the OR is done independently for each type of exception; for packed computations this means 4 sub-operands and for scalar computations this means 1 suboperand (the lowest one). 11.7.2.3. SOFTWARE EXCEPTION HANDLING - UNMASKED EXCEPTIONS An application must ensure that the operating system supports unmasked exceptions before unmasking any of the exceptions in the MXCSR (refer to Section 9.5.1., “Detecting Support for Streaming SIMD Extensions Using the CPUID Instruction” Chapter 9, Programming with the Streaming SIMD Extensions, Volume 1 of the Programmer’s Reference Manual). If th...
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