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Bits 12 7 configure numerical exception masking an

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Unformatted text preview: technology instructions apply to the Streaming SIMD Extensions. Hence everything referenced in chapter 10 relating to MMX™ technology and system programming is applicable to the SIMD-integer instructions in the Streaming SIMD Extensions. 11.3. NEW PENTIUM® III PROCESSOR REGISTERS The Pentium® III Processor introduced a set of 128-bit general-purpose registers. These registers are directly addressable and can be used to hold data only. In addition, the Pentium® III Processor also introduced a new control/status register (MXCSR) that is used to flag exceptions resulting from computations involving the SIMD floating-point registers, mask/unmask exceptions, and control the rounding and flush-to-zero modes. These registers are described more completely in the following sections. 11-1 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING 11.3.1. SIMD Floating-point Registers Streaming SIMD Extensions provides eight 128-bit general-purpose registers, each of which can be directly addressed. These registers are new state, and require support from the operating system to use them. The SIMD floating-point registers can hold packed 128-bit data. The SIMD floating-point instructions access the SIMD floating-point registers directly using the register names XMM0 to XMM7 (Table 11-1). These registers can be used to perform calculations on data. They cannot be used to address memory; addressing is accomplished by using the integer registers and existing IA addressing modes. The contents of SIMD floating-point registers are cleared upon reset. There is a new control/status register MXCSR which is used to mask/unmask numerical exception handling, to set rounding modes, to set the flush-to-zero mode, and to view status flags. Table 11-1. SIMD Floating-point Register Set 128 97 96 64 63 32 31 0 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 11.3.2. SIMD Floating-point Control/Status Registers The control/status register is used to enable masked/unmasked numerical exception handling, to set rounding modes, to set the flush-to-zero mode, and to view status flags. The contents of this register can be loaded with the LDMXCSR and FXRSTOR instructions and stored in memory with the STMXCSR and FXSAVE instructions. Figure 11-1 shows the format and encoding of the fields in the MXCSR. 11-2 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING 31-16 Reserved 15 FR ZC R C P M U M 10 O M Z M D M I M R s v d 5 P E U E O E Z E D E 0 I E Figure 11-1. Streaming SIMD Extensions Control/Status Register Format Bits 5-0 indicate whether a Streaming SIMD Extensions numerical exception has been detected. They are “sticky” flags, and can be cleared by using the LDMXCSR instruction to write zeroes to these fields. If a LDMXCSR instruction clears a mask bit and sets the corresponding exception flag bit, an exception will not be generated because of this change. This type of exception will occur only upon the next Streaming SIMD Extensions instruction to cause it. Streaming SIMD Extensions use only one exception flag for each exception. There is no provision for individual exception reporting within a packed data type. In situations where multiple identical exceptions occur within the same instruction, the associated exception flag is updated and indicates that at least one of these conditions happened. These flags are cleared upon reset. Bits 12-7 configure numerical exception masking; an exception type is masked if the corresponding bit is set and it is unmasked if the bit is clear. These bits are set upon reset, meaning that all numerical exceptions are masked. Bits 14-13 encode the rounding control, which provides for the common round to nearest mode, as well as directed rounding and true chop (refer to Section 11.3.2.1., “Rounding Control Field”). The rounding control is set to round to nearest upon reset. Bit 15 (FZ) is used to turn on the flush-to-zero mode (refer to Section 11.3.2.2., “Flush-toZero”). This bit is cleared upon reset, disabling the flush-to-zero mode. The other bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared; attempting to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions, will result in a general protection exception. 11.3.2.1. ROUNDING CONTROL FIELD The rounding control (RC) field of MXCSR (bits 13 and 14) controls how the results of floatingpoint instructions are rounded. Four rounding modes are supported: round to nearest, round up, round down, and round toward zero (see Table 11-2). Round to nearest is the default rounding mode and is suitable for most applications. It provides the most accurate and statistically unbiased estimate of the true result. 11-3 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING Table 11-2. Rounding Control Field (RC) Rounding Mode Round to nearest (even) Round down (toward −∞) Round up (toward +∞) Round toward zero (truncate) RC Field Setting 00B Description Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is the even value (that is, the one with the least-significant bit of zero). Rounded result is closest to, but no greater than the infinitely precise result. Rounded result is closest to, but no less than t...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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