Unformatted text preview: : • Alignment-check exception (#AC, interrupt 17)—New exception. Reports unaligned memory references when alignment checking is being performed. The following exceptions and/or exception conditions were added to the Intel386™ processor: • Divide-error exception (#DE, interrupt 0) — Change in exception handling. Divide-error exceptions on the Intel386™ processors always leave the saved CS:IP value pointing to the instruction that failed. On the 8086 processor, the CS:IP value points to the next instruction. — Change in exception handling. The Intel386™ processors can generate the largest negative number as a quotient for the IDIV instruction (80H and 8000H). The 8086 processor generates a divide-error exception instead. • • Invalid-opcode exception (#UD, interrupt 6)—New exception condition added. Improper use of the LOCK instruction prefix can generate an invalid-opcode exception. Page-fault exception (#PF, interrupt 14)—New exception condition added. If paging is enabled in a 16-bit program, a page-fault exception can be generated as follows. Paging can be used in a system with 16-bit tasks if all tasks use the same page directory. Because there is no place in a 16-bit TSS to store the PDBR register, switching to a 16-bit task does not change the value of the PDBR register. Tasks ported from the Intel 286 processor should be given 32-bit TSSs so they can make full use of paging. 18-26 INTEL ARCHITECTURE COMPATIBILITY • General-protection exception (#GP, interrupt 13)—New exception condition added. The Intel386™ processor sets a limit of 15 bytes on instruction length. The only way to violate this limit is by putting redundant prefixes before an instruction. A general-protection exception is generated if the limit on instruction length is violated. The 8086 processor has no instruction length limit. 18.19.1. Machine-Check Architecture
The Pentium® Pro processor introduced a new architecture to the Intel Architecture for handling and reporting on machine-check exceptions. This machine-check architecture (described in detail in Chapter 13, Machine-Check Architecture) greatly expands the ability of the processor to report on internal hardware errors. 18.19.2. Priority OF Exceptions
The priority of exceptions are broken down into several major categories: 1. Traps on the previous instruction 2. External interrupts 3. Faults on fetching the next instruction 4. Faults in decoding the next instruction 5. Faults on executing an instruction There are no changes in the priority of these major categories between the different processors, however, exceptions within these categories are implementation dependent and may change from processor to processor. 18.20. INTERRUPTS
The following differences in handling interrupts are found among the Intel Architecture processors. 18.20.1. Interrupt Propagation Delay
External hardware interrupts may be recognized on different instruction boundaries on the P6 family, Pentium®, Intel486™, and Intel386™ processors, due to the superscaler designs of the P6 family and Pentium® processors. Therefore, the EIP pushed onto the stack when servicing an interrupt may be different for the P6 family, Pentium®, Intel486™, and Intel386™ processors. 18-27 INTEL ARCHITECTURE COMPATIBILITY 18.20.2. NMI Interrupts
After an NMI interrupt is recognized by the P6 family, Pentium®, Intel486™, Intel386™, and Intel 286 processors, the NMI interrupt is masked until the first IRET instruction is executed, unlike the 8086 processor. 18.20.3. IDT Limit
The LIDT instruction can be used to set a limit on the size of the IDT. A double-fault exception (#DF) is generated if an interrupt or exception attempts to read a vector beyond the limit. Shutdown then occurs on the 32-bit Intel Architecture processors if the double-fault handler vector is beyond the limit. (The 8086 processor does not have a shutdown mode nor a limit.) 18.21. TASK SWITCHING AND TSS
This section identifies the implementation differences of task switching, additions to the TSS and the handling of TSSs and TSS segment selectors. 18.21.1. P6 Family and Pentium® Processor TSS
When the virtual mode extensions are enabled (by setting the VME flag in control register CR4), the TSS in the P6 family and Pentium® processors contain an interrupt redirection bit map, which is used in virtual-8086 mode to redirect interrupts back to an 8086 program. 18.21.2. TSS Selector Writes
During task state saves, the Intel486™ processor writes 2-byte segment selectors into a 32-bit TSS, leaving the upper 16 bits undefined. For performance reasons, the P6 family and Pentium® processors write 4-byte segment selectors into the TSS, with the upper 2 bytes being 0. For compatibility reasons, code should not depend on the value of the upper 16 bits of the selector in the TSS. 18.21.3. Order of Reads/Writes to the TSS
The order of reads and writes into the TSS is processor dependent. The P6 family and Pentium® processors may generate different page-fault addresses in control register CR2 in the same TSS area than the Intel486™ and Intel386™ processors, if a TSS crosses a page boundary (which is not...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10