Unformatted text preview: odels of memory organization and describes the register set used by applications. Chapter 4 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack and the mechanisms provided for making procedure calls and for servicing interrupts and exceptions. Chapter 5 — Data Types and Addressing Modes. Describes the data types and addressing modes recognized by the processor. Chapter 6 — Instruction Set Summary. Gives an overview of all the Intel Architecture instructions except those executed by the processor’s floating-point unit. The instructions are presented in functionally related groups. Chapter 7 — Floating-Point Unit. Describes the Intel Architecture floating-point unit, including the floating-point registers and data types; gives an overview of the floating-point instruction set; and describes the processor’s floating-point exception conditions. Chapter 8 — Programming with the Intel MMX™ Technology. Describes the Intel MMX™ technology, including MMX™ registers and data types, and gives an overview of the MMX™ instruction set. Chapter 9 — Programming with the Streaming SIMD Extensions. Describes the Intel Streaming SIMD Extensions, including the registers and data types. Chapter 10— Input/Output. Describes the processor’s I/O architecture, including I/O port addressing, the I/O instructions, and the I/O protection mechanism. Chapter 11 — Processor Identification and Feature Determination. Describes how to determine the CPU type and the features that are available in the processor. Appendix A — EFLAGS Cross-Reference. Summarizes how the Intel Architecture instructions affect the flags in the EFLAGS register. Appendix B — EFLAGS Condition Codes. Summarizes how the conditional jump, move, and byte set on condition code instructions use the condition code flags (OF, CF, ZF, SF, and PF) in the EFLAGS register. Appendix C — Floating-Point Exceptions Summary. Summarizes the exceptions that can be raised by floating-point instructions. Appendix D — SIMD Floating-Point Exceptions Summary. Provides the Streaming SIMD Extensions mnemonics, and the exceptions that each instruction can cause. Appendix E — Guidelines for Writing FPU Exception Handlers. Describes how to design and write MS-DOS* compatible exception handling facilities for FPU and SIMD floating-point exceptions, including both software and hardware requirements and assembly-language code 1-4 ABOUT THIS MANUAL examples. This appendix also describes general techniques for writing robust FPU exception handlers. Appendix F — Guidelines for Writing SIMD-FP Exception Handlers. Provides guidelines for the Streaming SIMD Extensions instructions that can generate numeric (floating-point) exceptions, and gives an overview of the necessary support for handling such exceptions. 1.4. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCE The contents of the Intel Architecture Software Developer’s Manual, Volume 2, are as follows: Chapter 1 — About This Manual. Gives an overview of all three volumes of the Intel Architecture Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers. Chapter 2 — Instruction Format. Describes the machine-level instruction format used for all Intel Architecture instructions and gives the allowable encodings of prefixes, the operand-identifier byte (ModR/M byte), the addressing-mode specifier byte (SIB byte), and the displacement and immediate bytes. Chapter 3 — Instruction Set Reference. Describes each of the Intel Architecture instructions in detail, including an algorithmic description of operations, the effect on flags, the effect of operand- and address-size attributes, and the exceptions that may be generated. The instructions are arranged in alphabetical order. The FPU, MMX™ Technology instructions, and Streaming SIMD Extensions are included in this chapter. Appendix A — Opcode Map. Gives an opcode map for the Intel Architecture instruction set. Appendix B — Instruction Formats and Encodings. Gives the binary encoding of each form of each Intel Architecture instruction. Appendix C — Compiler Intrinsics and Functional Equivalents. Gives the Intel C/C++ compiler intrinsics and functional equivalents for the MMX™ Technology instructions and Streaming SIMD Extensions. 1.5. NOTATIONAL CONVENTIONS This manual uses special notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal numbers. A review of this notation makes the manual easier to read. 1-5 ABOUT THIS MANUAL 1.5.1. Bit and Byte Order In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. Intel Architecture processors are “little endian” machines; this means the bytes of a word are numbered starting from the least signifi...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10