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Counter 0 only 11h fpassist 00h number of floating

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Unformatted text preview: the instruction length decoder is stalled. Number of L2 instruction fetches. This event indicates that a normal instruction fetch was received by the L2. The count includes only L2 cacheable instruction fetches; it does not include UC instruction fetches. It does not include ITLB miss accesses. L2 Cache1 28H L2_IFETCH MESI 0FH 29H L2_LD MESI 0FH Number of L2 data loads. This event indicates that a normal, unlocked, load memory access was received by the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other nonmemory accesses, or memory accesses such as UC/WT memory accesses. It does include L2 cacheable TLB miss memory accesses. 2AH L2_ST MESI 0FH Number of L2 data stores. This event indicates that a normal, unlocked, store memory access was received by the L2. Specifically, it indicates that the DCU sent a read-for-ownership request to the L2. It also includes Invalid to Modified requests sent by the DCU to the L2. It includes only L2 cacheable memory accesses; it does not include I/O accesses, other nonmemory accesses, or memory accesses such as UC/WT memory accesses. It includes TLB miss memory accesses. 24H L2_LINES_IN 00H Number of lines allocated in the L2. A-3 PERFORMANCE-MONITORING EVENTS Table A-1. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.) Unit Event Num. 26H 25H 27H Mnemonic Event Name L2_LINES_OUT L2_M_LINES_INM L2_M_LINES_OUTM Unit Mask 00H 00H 00H Description Number of lines removed from the L2 for any reason. Number of modified lines allocated in the L2. Number of modified lines removed from the L2 for any reason. Total number of L2 requests. Number of L2 address strobes. Number of cycles during which the L2 cache data bus was busy. Number of cycles during which the data bus was busy transferring read data from L2 to the processor. Number of clocks during which DRDY# is asserted. Utilization of the external system data bus during data transfers. Comments 2EH 21H 22H 23H L2_RQSTS L2_ADS L2_DBUS_BUSY L2_DBUS_BUSY_RD MESI 0FH 00H 00H 00H External Bus Logic (EBL)2 62H BUS_DRDY_ CLOCKS 00H (Self) 20H (Any) Unit Mask = 00H counts bus clocks when the processor is driving DRDY#. Unit Mask = 20H counts in processor clocks when any agent is driving DRDY#. 63H BUS_LOCK_ CLOCKS 00H (Self) 20H (Any) 00H (Self) Number of clocks during which LOCK# is asserted on the external system bus.3 Number of bus requests outstanding. This counter is incremented by the number of cacheable read bus requests outstanding in any given cycle. Always counts in processor clocks. 60H BUS_REQ_ OUTSTANDING Counts only DCU fullline cacheable reads, not RFOs, writes, instruction fetches, or anything else. Counts “waiting for bus to complete” (last data chunk received). 65H BUS_TRAN_BRD 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) Number of burst read transactions. 66H BUS_TRAN_RFO Number of completed read for ownership transactions. 67H BUS_TRANS_WB Number of completed write back transactions. 68H BUS_TRAN_ IFETCH Number of completed instruction fetch transactions. A-4 PERFORMANCE-MONITORING EVENTS Table A-1. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.) Unit Event Num. 69H Mnemonic Event Name BUS_TRAN_INVAL Unit Mask 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) 00H (Self) 20H (Any) Description Number of completed invalidate transactions. Comments 6AH BUS_TRAN_PWR Number of completed partial write transactions. 6BH BUS_TRANS_P Number of completed partial transactions. 6CH BUS_TRANS_IO Number of completed I/O transactions. 6DH BUS_TRAN_DEF Number of completed deferred transactions. 6EH BUS_TRAN_BURST Number of completed burst transactions. 70H BUS_TRAN_ANY Number of all completed bus transactions. Address bus utilization can be calculated knowing the minimum address bus occupancy. Includes special cycles, etc. 6FH BUS_TRAN_MEM 00H (Self) 20H (Any) 00H (Self) 00H (Self) Number of completed memory transactions. 64H BUS_DATA_RCV Number of bus clock cycles during which this processor is receiving data. Number of bus clock cycles during which this processor is driving the BNR# pin. 61H BUS_BNR_DRV A-5 PERFORMANCE-MONITORING EVENTS Table A-1. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.) Unit Event Num. 7AH Mnemonic Event Name BUS_HIT_DRV Unit Mask 00H (Self) Description Number of bus clock cycles during which this processor is driving the HIT# pin. Comments Includes cycles due to snoop stalls. The event counts correctly, but the BPMi pins function as follows based on the setting of the PC bits (bit 19 in the PerfEvtSel0 and PerfEvtSel1 registers): If the core-clock-to- busclock ratio is 2:1 or 3:1, and a PC bit is set, the BPMipins will be asserted for a single clock when the counters overflow. If the PC bit is clear, the processor toggles the BPMipins when the counter overflows. If the clock ratio is not 2:1 or 3:1, the BPMi pins will not function for these performan...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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