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Debug registers 15 3 debugging and performance

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Unformatted text preview: sters (MSRs). The debug registers of the Intel Architecture processors hold the addresses of memory and I/O locations, called breakpoints. Breakpoints are user-selected locations in a program, a data-storage area in memory, or specific I/O ports where a programmer or system designer wishes to halt execution of a program and examine the state of the processor by invoking debugger software. A debug exception (#DB) is generated when a memory or I/O access is made to one of these breakpoint addresses. A breakpoint is specified for a particular form of memory or I/O access, such as a memory read and/or write operation or an I/O read and/or write operation. The debug registers support both instruction breakpoints and data breakpoints. The MSRs (which were introduced into the Intel Architecture in the P6 family processors) monitor branches, interrupts, and exceptions and record the addresses of the last branch, interrupt or exception taken and the last branch taken before an interrupt or exception. 15.1. OVERVIEW OF THE DEBUGGING SUPPORT FACILITIES The following processor facilities support debugging and performance monitoring: • • • • • • • Debug exception (#DB)—Transfers program control to a debugger procedure or task when a debug event occurs. Breakpoint exception (#BP)—Transfers program control to a debugger procedure or task when an INT 3 instruction is executed. Breakpoint-address registers (DB0 through DB3)—Specifies the addresses of up to 4 breakpoints. Debug status register (DB6)—Reports the conditions that were in effect when a debug or breakpoint exception was generated. Debug control register (DB7)—Specifies the forms of memory or I/O access that cause breakpoints to be generated. DebugCtlMSR register—Enables last branch, interrupt, and exception recording; taken branch traps; the breakpoint reporting pins; and trace messages. LastBranchToIP and LastBranchFromIP MSRs—Specifies the source and destination addresses of the last branch, interrupt, or exception taken. The address saved is the offset in the code segment of the branch (source) or target (destination) instruction. 15-1 DEBUGGING AND PERFORMANCE MONITORING • LastExceptionToIP and LastExceptionFromIP MSRs—Specifies the source and destination addresses of the last branch that was taken prior to an exception or interrupt being generated. The address saved is the offset in the code segment of the branch (source) or target (destination) instruction. T (trap) flag, TSS—Generates a debug exception (#DB) when an attempt is made to switch to a task with the T flag set in its TSS. RF (resume) flag, EFLAGS register— Suppresses multiple exceptions to the same instruction. TF (trap) flag, EFLAGS register—Generates a debug exception (#DB) after every execution of an instruction. Breakpoint instruction (INT 3)—Generates a breakpoint exception (#BP), which transfers program control to the debugger procedure or task. This instruction is an alternative way to set code breakpoints. It is especially useful when more than four breakpoints are desired, or when breakpoints are being placed in the source code. • • • • These facilities allow a debugger to be called either as a separate task or as a procedure in the context of the current program or task. The following conditions can be used to invoke the debugger: • • • • • • • • • Task switch to a specific task. Execution of the breakpoint instruction. Execution of any instruction. Execution of an instruction at a specified address. Read or write of a byte, word, or doubleword at a specified memory address. Write to a byte, word, or doubleword at a specified memory address. Input of a byte, word, or doubleword at a specified I/O address. Output of a byte, word, or doubleword at a specified I/O address. Attempt to change the contents of a debug register. 15.2. DEBUG REGISTERS The eight debug registers (refer to Figure 15-1) control the debug operation of the processor. These registers can be written to and read using the move to or from debug register form of the MOV instruction. A debug register may be the source or destination operand for one of these instructions. The debug registers are privileged resources; a MOV instruction that accesses these registers can only be executed in real-address mode, in SMM, or in protected mode at a CPL of 0. An attempt to read or write the debug registers from any other privilege level generates a general-protection exception (#GP). 15-2 DEBUGGING AND PERFORMANCE MONITORING 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R s LEN R/W LEN R/W LEN R/W LEN R/W 0 0 G 0 0 1 G L G L G L G L G L DR7 vEE33221 100 3 3 2 2 1 1 0 0 D d 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved (set to 1) BBB 0 1 1 1 1 1 1 11 B BB B DR6 TSD 3210 0 31 Reserved DR5 0 31 Reserved DR4 0 31 Breakpoint 3 Linear Address DR3 0 31 Breakpoint 2 Linear Address DR2 0 31 Breakpoint 1 Linear Address DR1 0 31 Breakpoint 0 Linear Address DR0 Reserved Bits, DO NOT DEFINE Figure 15-1. Debug Registers 15-3 DEBUGGING AND PERFORMANCE MONITORING The p...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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