This preview shows page 1. Sign up to view the full content.
Unformatted text preview: the focus of an interrupt if it is currently servicing that interrupt or if it has a pending request for that interrupt. 7-22 MULTIPLE-PROCESSOR MANAGEMENT 7.5.11. Local Vector Table
The local APIC contains a local vector table (LVT), specifying interrupt delivery and status information for the local interrupts. The information contained in this table includes the interrupt’s associated vector, delivery mode, status bits and other data as shown in Figure 7-8. The LVT incorporates five 32-bit entries: one for the timer, one each for the two local interrupt (LINT0 and LINT1) pins, one for the error interrupt, and (in the P6 family processors) one for the performance-monitoring counter interrupt. The fields in the LVT are as follows: Vector Delivery Mode Interrupt vector number. Defined only for local interrupt entries 1 and 2 and the performancemonitoring counter. The timer and the error status register (ESR) generate only edge triggered maskable hardware interrupts to the local processor. The delivery mode field does not exist for the timer and error interrupts. The performance-monitoring counter LVT may be programmed with a Deliver Mode equal to Fixed or NMI only. Note that certain delivery modes will only operate as intended when used in conjunction with a specific Trigger Mode. The allowable delivery modes are as follows: 000 (Fixed) Delivers the interrupt, received on the local interrupt pin, to this processor as specified in the corresponding LVT entry. The trigger mode can be edge or level. Note, if the processor is not used in conjunction with an I/O APIC, the fixed delivery mode may be software programmed for an edgetriggered interrupt, but the P6 family processors implementation will always operate in a leveltriggered mode. Delivers the interrupt, received on the local interrupt pin, to this processor as an NMI interrupt. The vector information is ignored. The NMI interrupt is treated as edge-triggered, even if programmed otherwise. Note that the NMI may be masked. It is the software's responsibility to program the LVT mask bit according to the desired behavior of NMI. Delivers the interrupt, received on the local interrupt pin, to this processor and responds as if the interrupt originated in an externally connected (8259A-compatible) interrupt controller. A special INTA bus cycle corresponding to ExtINT, is routed to the external controller. The latter is expected to supply the vector information. When the delivery mode is ExtINT, the trigger-mode is 100 (NMI) 111 (ExtINT) 7-23 MULTIPLE-PROCESSOR MANAGEMENT level-triggered, regardless of how the APIC triggering mode is programmed. The APIC architecture supports only one ExtINT source in a system, usually contained in the compatibility bridge. 31 18 17 16 15 13 12 11 87 0 Timer Timer Mode 0: One-shot 1: Periodic Vector Address: FEE0 0320H Value after Reset: 0001 0000H Delivery Status 0: Idle 1: Send Pending Mask 0: Not Masked 1: Masked Interrupt Input Pin Polarity Remote IRR Trigger Mode 0: Edge 1: Level Delivery Mode 000: Fixed 100: NMI 111: ExtlNT All other combinations are Reserved 31 17 11 10 87 0 LINT0 LINT1 ERROR PCINT
16 15 14 13 12 Vector Vector Vector Vector Address: FEE0 0350H Address: FEE0 0360H Address: FEE0 0370H Address: FEE0 0340H Value After Reset: 0001 0000H Reserved Figure 7-8. Local Vector Table (LVT) 7-24 MULTIPLE-PROCESSOR MANAGEMENT Delivery Status (read only) Holds the current status of interrupt delivery. Two states are defined: 0 (Idle) There is currently no activity for this interrupt, or the previous interrupt from this source has completed. 1 (Send Pending) Indicates that the interrupt transmission has started, but has not yet been completely accepted. Interrupt Input Pin Polarity Specifies the polarity of the corresponding interrupt pin: (0) active high or (1) active low. Remote Interrupt Request Register (IRR) Bit Used for level triggered interrupts only; its meaning is undefined for edge triggered interrupts. For level triggered interrupts, the bit is set when the logic of the local APIC accepts the interrupt. The remote IRR bit is reset when an EOI command is received from the processor. Trigger Mode Selects the trigger mode for the local interrupt pins when the delivery mode is Fixed: (0) edge sensitive and (1) level sensitive. When the delivery mode is NMI, the trigger mode is always level sensitive; when the delivery mode is ExtINT, the trigger mode is always level sensitive. The timer and error interrupts are always treated as edge sensitive. Interrupt mask: (0) enables reception of the interrupt and (1) inhibits reception of the interrupt. Selects the timer mode: (0) one-shot and (1) periodic (refer to Section 7.5.18., “Timer”). Mask Timer Mode 7.5.12. Interprocessor and Self-Interrupts
A processor generates interprocessor interrupts by writing into the interrupt command register (ICR) of its local APIC (refer to Figure 7-9). The processor may use the ICR for self interrupts or for interrupting other processors (for example, to forward device inte...
View Full Document
This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10