IntelSoftwareDevelopersManual

Enables the machine check exception when set disables

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: nce Monitoring, for more information on the function of this flag. Page Size Extensions (bit 4 of CR4). Enables 4-MByte pages when set; restricts pages to 4 KBytes when clear. Refer to Section 3.6.1., “Paging Options” in Chapter 3, Protected-Mode Memory Management for more information about the use of this flag. Physical Address Extension (bit 5 of CR4). Enables paging mechanism to reference 36-bit physical addresses when set; restricts physical addresses to 32 bits when clear. Refer to Section 3.8., “Physical Address Extension” in Chapter 3, Protected-Mode Memory Management for more information about the physical address extension. Machine-Check Enable (bit 6 of CR4). Enables the machine-check exception when set; disables the machine-check exception when clear. Refer to Chapter 13, MachineCheck Architecture, for more information about the machine-check exception and machine- check architecture. Page Global Enable (bit 7 of CR4). (Introduced in the P6 family processors.) Enables the global page feature when set; disables the global page feature when clear. The global page feature allows frequently used or shared pages to be marked as global to all users (done with the global flag, bit 8, in a page-directory or page-table entry). Global pages are not flushed from the translation-lookaside buffer (TLB) on a task switch or a write to register CR3. In addition, the bit must not be enabled before paging PVI TSD DE PSE PAE MCE PGE 2-17 SYSTEM ARCHITECTURE OVERVIEW is enabled via CR0.PG. Program correctness may be affected by reversing this sequence, and processor performance will be impacted. Refer to Section 3.7., “Translation Lookaside Buffers (TLBs)” in Chapter 3, Protected-Mode Memory Management for more information on the use of this bit. PCE Performance-Monitoring Counter Enable (bit 8 of CR4). Enables execution of the RDPMC instruction for programs or procedures running at any protection level when set; RDPMC instruction can be executed only at protection level 0 when clear. OSFXSR Operating Sytsem FXSAVE/FXRSTOR Support (bit 9 of CR4). The operating system will set this bit if both the CPU and the OS support the use of FXSAVE/FXRSTOR for use during context switches. OSXMMEXCPT Operating System Unmasked Exception Support (bit 10 of CR4). The operating system will set this bit if it provides support for unmasked SIMD floating-point exceptions. 2.5.1. CPUID Qualification of Control Register Flags The VME, PVI, TSD, DE, PSE, PAE, MCE, PGE, PCE, OSFXSR, and OSXMMCEPT flags in control register CR4 are model specific. All of these flags (except PCE) can be qualified with the CPUID instruction to determine if they are implemented on the processor before they are used. 2.6. SYSTEM INSTRUCTION SUMMARY The system instructions handle system-level functions such as loading system registers, managing the cache, managing interrupts, or setting up the debug registers. Many of these instructions can be executed only by operating-system or executive procedures (that is, procedures running at privilege level 0). Others can be executed at any privilege level and are thus available to application programs. Table 2-2 lists the system instructions and indicates whether they are available and useful for application programs. These instructions are described in detail in Chapter 3, Instruction Set Reference, of the Intel Architecture Software Developer’s Manual, Volume 2. 2-18 SYSTEM ARCHITECTURE OVERVIEW : Table 2-2. Summary of System Instructions Instruction LLDT SLDT LGDT SGDT LTR STR LIDT SIDT MOV CRn SMSW LMSW CLTS ARPL LAR LSL VERR VERW MOV DBn INVD WBINVD INVLPG HLT LOCK (Prefix) RSM RDMSR3 WRMSR RDTSC 3 3 Description Load LDT Register Store LDT Register Load GDT Register Store GDT Register Load Task Register Store Task Register Load IDT Register Store IDT Register Load and store control registers Store MSW Load MSW Clear TS flag in CR0 Adjust RPL Load Access Rights Load Segment Limit Verify for Reading Verify for Writing Load and store debug registers Invalidate cache, no writeback Invalidate cache, with writeback Invalidate TLB entry Halt Processor Bus Lock Return from system management mode Read Model-Specific Registers Write Model-Specific Registers Read Performance-Monitoring Counter Read Time-Stamp Counter Load MXCSR Register Store MXCSR Resister Useful to Application? No No No No No No No No Yes Yes No No Yes1 Yes Yes Yes Yes No No No No No Yes No No No Yes Yes Yes Yes No Protected from Application? Yes Yes No Yes No Yes No Yes (load only) No Yes Yes No No No No No Yes Yes Yes Yes Yes No Yes Yes Yes Yes2 Yes2 No No RDPMC4 LDMXCSR5 STMXCSR NOTES: 5 1. Useful to application programs running at a CPL of 1 or 2. 2. The TSD and PCE flags in control register CR4 control access to these instructions by application programs running at a CPL of 3. 3. These instructions were introduced into the Intel Architecture with the Pentium® processor. 4. This instruction was introduced into the Intel Architecture with the Pentium® Pro processor and the Pentium processor with MMX™...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

Ask a homework question - tutors are online