Fault fault abort fault type fault fault trap

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: or task to be continued without loss of program continuity. The return address for the trap handler points to the instruction to be executed after the trapping instruction. An abort is an exception that does not always report the precise location of the instruction causing the exception and does not allow restart of the program or task that caused the exception. Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables. Aborts 5-5 INTERRUPT AND EXCEPTION HANDLING Table 5-1. Protected-Mode Exceptions and Interrupts Vector No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-31 32255 #TS #NP #SS #GP #PF — #MF #AC #MC #XF — — Mnemonic #DE #DB — #BP #OF #BR #UD #NM #DF Description Divide Error Debug NMI Interrupt Breakpoint Overflow BOUND Range Exceeded Invalid Opcode (Undefined Opcode) Device Not Available (No Math Coprocessor) Double Fault Coprocessor Segment Overrun (reserved) Invalid TSS Segment Not Present Stack-Segment Fault General Protection Page Fault (Intel reserved. Do not use.) Floating-Point Error (Math Fault) Alignment Check Machine Check Streaming SIMD Extensions Intel reserved. Do not use. User Defined (Nonreserved) Interrupts Interrupt External interrupt or INT n instruction. Fault Fault Abort Fault Type Fault Fault/ Trap Interrupt Trap Trap Fault Fault Fault Abort Fault Fault Fault Fault Fault Fault Error Code No No No No No No No No Yes (Zero) No Yes Yes Yes Yes Yes No No Yes (Zero) No No Floating-point or WAIT/FWAIT instruction. Any data reference in memory.3 Error codes (if any) and source are model dependent.4 SIMD floating-point instructions5 Source DIV and IDIV instructions. Any code or data reference or the INT 1 instruction. Nonmaskable external interrupt. INT 3 instruction. INTO instruction. BOUND instruction. UD2 instruction or reserved opcode.1 Floating-point or WAIT/FWAIT instruction. Any instruction that can generate an exception, an NMI, or an INTR. Floating-point instruction.2 Task switch or TSS access. Loading segment registers or accessing system segments. Stack operations and SS register loads. Any memory reference and other protection checks. Any memory reference. NOTES: 1. The UD2 instruction was introduced in the Pentium® Pro processor. 2. Intel Architecture processors after the Intel386™ processor do not generate this exception. 3. This exception was introduced in the Intel486™ processor. 4. This exception was introduced in the Pentium® processor and enhanced in the P6 family processors. 5. This exception was introduced in the Pentium® III processor. 5-6 INTERRUPT AND EXCEPTION HANDLING 5.4. PROGRAM OR TASK RESTART To allow restarting of program or task following the handling of an exception or an interrupt, all exceptions except aborts are guaranteed to report the exception on a precise instruction boundary, and all interrupts are guaranteed to be taken on an instruction boundary. For fault-class exceptions, the return instruction pointer that the processor saves when it generates the exception points to the faulting instruction. So, when a program or task is restarted following the handling of a fault, the faulting instruction is restarted (re-executed). Restarting the faulting instruction is commonly used to handle exceptions that are generated when access to an operand is blocked. The most common example of a fault is a page-fault exception (#PF) that occurs when a program or task references an operand in a page that is not in memory. When a page-fault exception occurs, the exception handler can load the page into memory and resume execution of the program or task by restarting the faulting instruction. To insure that this instruction restart is handled transparently to the currently executing program or task, the processor saves the necessary registers and stack pointers to allow it to restore itself to its state prior to the execution of the faulting instruction. For trap-class exceptions, the return instruction pointer points to the instruction following the trapping instruction. If a trap is detected during an instruction which transfers execution, the return instruction pointer reflects the transfer. For example, if a trap is detected while executing a JMP instruction, the return instruction pointer points to the destination of the JMP instruction, not to the next address past the JMP instruction. All trap exceptions allow program or task restart with no loss of continuity. For example, the overflow exception is a trapping exception. Here, the return instruction pointer points to the instruction following the INTO instruction that tested the OF (overflow) flag in the EFLAGS register. The trap handler for this exception resolves the overflow condition. Upon return from the trap handler, program or task execution continues at the next instruction following the INTO instruction. The abort-class exceptions do not support reliable restarting of the program or task. Abort handlers generally are designed to collect diagnostic information about the state of the processor when the abort exception occurred and then shut down the application and system as grace...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online