IntelSoftwareDevelopersManual

Field dest field dest field x self self self all inc

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Unformatted text preview: modes the level is 1. Used for the INIT level de-assert delivery mode only. 10: (all including self) The interrupt is sent to all processors in the system including the processor sending the interrupt. The APIC will broadcast a message with the destination field set to FH. Refer to Table 7-2 for description of supported modes. 11: (all excluding self) The interrupt is sent to all processors in the system with the exception of the processor sending the interrupt. The APIC will broadcast a message using 7-28 MULTIPLE-PROCESSOR MANAGEMENT the physical destination mode and destination field set to FH. Destination This field is only used when the destination shorthand field is set to “dest field”. If the destination mode is physical, then bits 56 through 59 contain the APIC ID. In logical destination mode, the interpretation of the 8-bit destination field depends on the DFR and LDR of the local APIC Units. Table 7-2 shows the valid combinations for the fields in the interrupt control register. Table 7-2. Valid Combinations for the APIC Interrupt Command Register Trigger Mode Edge Level Level Level Edge Level x Edge Level x Edge Level Level Level NOTES: 1. Valid. Treated as edge triggered if Level = 1 (assert), otherwise ignored. 2. Valid. Treated as edge triggered when Level = 1 (assert); when Level = 0 (deassert), treated as “INIT Level Deassert” message. Only INIT level deassert messages are allowed to have level = deassert. For all other messages the level must be “assert.” 3. Invalid. The behavior of the APIC is undefined. 4. X—Don’t care. Destination Mode Physical or Logical Physical or Logical Physical or Logical x4 x x x x x x x x x x Delivery Mode Fixed, Lowest Priority, NMI, SMI, INIT, Start-Up Fixed, Lowest Priority, NMI INIT SMI, Start-Up Fixed Fixed Lowest Priority, NMI, INIT, SMI, Start-Up Fixed Fixed Lowest Priority, NMI, INIT, SMI, Start-Up Fixed, Lowest Priority, NMI, INIT, SMI, Start-Up Fixed, Lowest Priority, NMI SMI, Start-Up INIT Valid/ Invalid Valid 1 2 Invalid3 Valid 1 Invalid3 Valid 1 Invalid Valid 1 Invalid 2 3 3 Destination Shorthand Dest. Field Dest. field Dest. Field x Self Self Self All inc Self All inc Self All inc Self All excl Self All excl Self All excl Self All excl Self 7-29 MULTIPLE-PROCESSOR MANAGEMENT 7.5.13. Interrupt Acceptance Three 256-bit read-only registers (the IRR, ISR, and TMR registers) are involved in the interrupt acceptance logic (refer to Figure 7-10). The 256 bits represents the 256 possible vectors. Because vectors 0 through 15 are reserved, so are bits 0 through 15 in these registers. The functions of the three registers are as follows: TMR (trigger mode register) Upon acceptance of an interrupt, the corresponding TMR bit is cleared for edge triggered interrupts and set for level interrupts. If the TMR bit is set, the local APIC sends an EOI message to all I/O APICs as a result of software issuing an EOI command (refer to Section 7.5.13.6., “End-Of-Interrupt (EOI)” for a description of the EOI register). 255 16 15 0 Reserved Reserved Reserved Addresses: IRR FEE0 0200H - FEE0 0270H ISR FEE0 0100H - FEE0 0170H TMR FEE0 0180H - FEE0 01F0H Value after reset: 0H IRR ISR TMR Figure 7-10. IRR, ISR and TMR Registers IRR (interrupt request register) Contains the active interrupt requests that have been accepted, but not yet dispensed by the current local APIC. A bit in IRR is set when the APIC accepts the interrupt. The IRR bit is cleared, and a corresponding ISR bit is set when the INTA cycle is issued. ISR (in-service register) Marks the interrupts that have been delivered to the processor, but have not been fully serviced yet, as an EOI has not yet been received from the processor. The ISR reflects the current state of the processor interrupt queue. The ISR bit for the highest priority IRR is set during the INTA cycle. During the EOI cycle, the highest priority ISR bit is cleared, and if the corresponding TMR bit was set, an EOI message is sent to all I/O APICs. 7.5.13.1. INTERRUPT ACCEPTANCE DECISION FLOW CHART The process that the APIC uses to accept an interrupt is shown in the flow chart in Figure 7-11. The response of the local APIC to the start-up IPI is explained in the Pentium® Pro Family Developer’s Manual, Volume 1. 7-30 MULTIPLE-PROCESSOR MANAGEMENT Wait to Receive Bus Message Discard Message No Belong to Destination? Yes Is it NMI/SMI/INIT / ExtINT? No Yes Accept Message Fixed Delivery Mode? Lowest Priority Set Status to Retry No Is Interrupt Slot Available? Am I Focus? No No Other Focus? Yes Accept Message Yes Yes Is Status a Retry? No Yes Discard Message Accept Message Is Interrupt Slot Available? Yes Set Status to Retry No Arbitrate No Am I Winner? Yes Accept Message Figure 7-11. Interrupt Acceptance Flow Chart for the Local APIC 7.5.13.2. TASK PRIORITY REGISTER Task priority register (TPR) provides a priority threshold mechanism for interrupting the processor (refer to Figure 7-12). Only interrupts whose priority is higher than that specified in the TPR will be serviced. Other interrupts are recorded and are serviced as soon a...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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