IntelSoftwareDevelopersManual

For all table entries except for page directory

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Unformatted text preview: rved (set to 0) 31 12 11 98 Base Addr. 543210 Page-Directory Base Address Avail. PP Reserved C W Res. 1 DT Page-Directory Entry (4-KByte Page Table) 63 36 35 32 Reserved (set to 0) 31 12 11 Base Addr. 9876543210 PPUR DTSW Page-Table Base Address Avail. 0 0 0 A C W / / P Page-Table Entry (4-KByte Page) 63 36 35 32 Reserved (set to 0) 31 12 11 Base Addr. 9876543210 PPUR DTSW Page Base Address Avail. G 0 D A C W / / P Figure 3-20. Format of Page-Directory-Pointer-Table, Page-Directory, and Page-Table Entries for 4-KByte Pages and 36-Bit Extended Physical Addresses The base physical address in an entry specifies the following, depending on the type of entry: • • • Page-directory-pointer-table entry—the physical address of the first byte of a 4-KByte page directory. Page-directory entry—the physical address of the first byte of a 4-KByte page table or a 2-MByte page. Page-table entry—the physical address of the first byte of a 4-KByte page. For all table entries (except for page-directory entries that point to 2-MByte or 4-MByte pages), the bits in the page base address are interpreted as the 24 most-significant bits of a 36-bit physical address, which forces page tables and pages to be aligned on 4-KByte boundaries. When a page-directory entry points to a 2-MByte or 4-MByte page, the base address is interpreted as the 15 most-significant bits of a 36-bit physical address, which forces pages to be aligned on 2MByte or 4-MByte boundaries. 3-34 PROTECTED-MODE MEMORY MANAGEMENT Page-Directory-Pointer-Table Entry 63 36 35 32 Reserved (set to 0) 31 12 11 98 Base Addr. 543210 Page Directory Base Address Avail. PP Reserved C W Res. 1 DT Page-Directory Entry (2- or 4-MByte Pages) 63 36 35 32 Reserved (set to 0) 31 21 20 12 11 Base Addr. 9876543210 PPUR DTSW Page Base Address Reserved (set to 0) Avail. G 1 D A C W / / P Figure 3-21. Format of Page-Directory-Pointer-Table and Page-Directory Entries for 2- or 4-MByte Pages and 36-Bit Extended Physical Addresses The present (P) flag (bit 0) in all page-directory-pointer-table entries must be set to 1 anytime extended physical addressing mode is enabled; that is, whenever the PAE flag (bit 5 in register CR4) and the PG flag (bit 31 in register CR0) are set. If the P flag is not set in all 4 page-directory-pointer-table entries in the page-directory-pointer table when extended physical addressing is enabled, a general-protection exception (#GP) is generated. The page size (PS) flag (bit 7) in a page-directory entry determines if the entry points to a page table or a 2-MByte or 4-MByte page. When this flag is clear, the entry points to a page table; when the flag is set, the entry points to a 2-MByte or 4-MByte page. This flag allows 4-KByte, 2-MByte, or 4-MByte pages to be mixed within one set of paging tables. Access (A) and dirty (D) flags (bits 5 and 6) are provided for table entries that point to pages. Bits 9, 10, and 11 in all the table entries for the physical address extension are available for use by software. (When the present flag is clear, bits 1 through 63 are available to software.) All bits in Figure 3-14 that are marked reserved or 0 should be set to 0 by software and not accessed by software. When the PSE and/or PAE flags in control register CR4 are set, the processor generates a page fault (#PF) if reserved bits in page-directory and page-table entries are not set to 0, and it generates a general-protection exception (#GP) if reserved bits in a page-directorypointer-table entry are not set to 0. 3.9. 36-BIT PAGE SIZE EXTENSION (PSE) The 36-bit PSE extends 36-bit physical address support to 4-MByte pages while maintaining a 4-byte page-directory entry. This approach provides a simple mechanism for operating system 3-35 PROTECTED-MODE MEMORY MANAGEMENT vendors to address physical memory above 4-GBytes without requiring major design changes, but has practical limitations with respect to demand paging. The P6 family of processors’ physical address extension (PAE) feature provides generic access to a 36-bit physical address space. However, it requires expansion of the page-directory and page-table entries to an 8-byte format (64 bit), and the addition of a page-directory-pointer table, resulting in another level of indirection to address translation. For P6-family processors that support the 36-bit PSE feature, the virtual memory architecture is extended to support 4-MByte page size granularity in combination with 36-bit physical addressing. Note that some P6-family processors do not support this feature. For information about determining a processor’s feature support, refer to the following documents: • • AP-485, Intel Processor Identification and the CPUID Instruction Addendum—Intel Architecture Software Developer’s Manual, Volume1: Basic Architecture For information about the virtual memory architecture features of P6-family processors, refer to Chapter 3 of the Intel Architecture Software Developer’s Manual, Volume3: System Programming Guide. 3.9.1. Description of the 36-bit PSE Feature The 36-bit PSE feature (PSE-36) is detected...
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