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Unformatted text preview: to flush the instruction prefetch unit of the Intel486™ processor by coding a jump instruction immediately after any write that modifies an instruction. The P6 family and Pentium® processors, however, check whether a write may modify an instruction that has been prefetched for execution. This check is based on the linear address of the instruction. If the linear address of an instruction is found to be present in the prefetch queue, the P6 family and Pentium® processors flush the prefetch queue, eliminating the need to code a jump instruction after any writes that modify an instruction. Because the linear address of the write is checked against the linear address of the instructions that have been prefetched, special care must be taken for self-modifying code to work correctly when the physical addresses of the instruction and the written data are the same, but the linear addresses differ. In such cases, it is necessary to execute a serializing operation to flush the prefetch queue after the write and before executing the modified instruction. Refer to Section 7.4., “Serializing Instructions” in Chapter 7, Multiple-Processor Management for more information on serializing instructions.
NOTE The check on linear addresses described above is not in practice a concern for compatibility. Applications that include self-modifying code use the same linear address for modifying and fetching the instruction. System software, such as a debugger, that might possibly modify an instruction using a different linear address than that used to fetch the instruction must execute a serializing operation, such as IRET, before the modified instruction is executed. 18.23. PAGING
This section identifies enhancements made to the paging mechanism and implementation differences in the paging mechanism for various Intel Architecture processors. 18-31 INTEL ARCHITECTURE COMPATIBILITY 18.23.1. Large Pages
The Pentium® processor extended the memory management/paging facilities of the Intel Architecture to allow large (4Mbytes) pages sizes (refer to Section 3.6.1., “Paging Options” in Chapter 3, Protected-Mode Memory Management). The initial P6 family processor (the Pentium® Pro processor) added a 2MByte page size to the Intel Architecture in conjunction with the physical address extension (PAE) feature (refer to Section 3.8., “Physical Address Extension” in Chapter 3, Protected-Mode Memory Management). The availability of large pages on any Intel Architecture processor can be determined via feature bit 3 (PSE) of register EDX after the CPUID instruction has been execution with an argument of 1. Intel processors that do not support the CPUID instruction do not support page size enhancements. (Refer to “CPUID—CPU Identification” in Chapter 3, Instruction Set Reference, of the Intel Architecture Software Developer’s Manual, Volume 2, and AP-485, Intel Processor Identification and the CPUID Instruction, for more information on the CPUID instruction.) 18.23.2. PCD and PWT Flags
The PCD and PWT flags were introduced to the Intel Architecture in the Intel486™ processor to control the caching of pages: • • PCD (page-level cache disable) flag—Controls caching on a page-by-page basis. PWT (page-level write-through) flag—Controls the write-through/writeback caching policy on a page-by-page basis. Since the internal cache of the Intel486™ processor is a write-through cache, it is not affected by the state of the PWT flag. 18.23.3. Enabling and Disabling Paging
Paging is enabled and disabled by loading a value into control register CR0 that modifies the PG flag. For backward and forward compatibility with all Intel Architecture processors, Intel recommends that the following operations be performed when enabling or disabling paging: 1. Execute a MOV CR0, REG instruction to either set (enable paging) or clear (disable paging) the PG flag. 2. Execute a near JMP instruction. The sequence bounded by the MOV and JMP instructions should be identity mapped (that is, the instructions should reside on a page whose linear and physical addresses are identical). For the P6 family processors, the MOV CR0, REG instruction is serializing, so the jump operation is not required. However, for backwards compatibility, the JMP instruction should still be included. 18-32 INTEL ARCHITECTURE COMPATIBILITY 18.24. STACK OPERATIONS
This section identifies the differences in the stack mechanism for the various Intel Architecture processors. 18.24.1. Selector Pushes and Pops
When pushing a segment selector onto the stack, the Intel486™ processor writes 2 bytes onto 4-byte stacks and decrements ESP by 4. The P6 family and Pentium® processors write 4 bytes, with the upper 2 bytes being zeros. When popping a segment selector from the stack, the Intel486™ processor reads only 2 bytes. The P6 family and Pentium® processors read 4 bytes and discard the upper 2 bytes. This operation may have an effect if the ESP is close to the stack-segment limit. On the P6 family and Pentium® processors, stack location at ESP plus 4 may be...
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- Spring '10