IntelSoftwareDevelopersManual

For example if a stack segment fault ss occurs due to

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Unformatted text preview: ion while the TS flag is set to 1, a device-not-available exception (#NM) is generated and the device-not-available exception handler executes the following pseudo-code. CR0.TS ← 0; FXSAVE “To SIMD floating-point State Save Area for Current SIMD Floating-point State Owner”; FXRSTOR “SIMD floating-point State From Current Task’s SIMD Floating-point State Save Area”; SIMF-fpStateOwner ← Current_Task; 11-10 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING This handler code performs the following tasks: • • • • Clears the TS flag. Saves the SIMD floating-point state in the state save area for the current SIMD floatingpoint state owner. Restores the SIMD floating-point state from the new task’s SIMD floating-point state save area. Updates the current SIMD floating-point state owner to be the current task. 11.7. EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING STREAMING SIMD EXTENSIONS INSTRUCTIONS Streaming SIMD Extensions can generate two kinds of exceptions: • • Non-numeric exceptions Numeric exceptions Streaming SIMD Extensions can generate the same type of memory access exceptions as the Intel Architecture instructions do. Some examples are: page fault, segment not present, and limit violations. Existing exception handlers can handle these types of exceptions without any code modification. The SIMD floating-point PREFETCH instruction hints will not generate any kind of exception and instead will be ignored. Streaming SIMD Extensions can generate the same six numeric exceptions that x87-FP instructions can generate. All Streaming SIMD Extensions numeric exceptions are reported independently of x87-FP numeric exceptions. Independent masking and unmasking of Streaming SIMD Extensions numeric exceptions is achieved by setting/resetting specific bits in the MXCSR register. The application must ensure that the OS can support unmasked SIMD floating-point exceptions before unmasking them. For more details, refer to Section 9.5.1., “Detecting Support for Streaming SIMD Extensions Using the CPUID Instruction” Chapter 9, Programming with the Streaming SIMD Extensions, in the Intel Architecture Software Developer’s Manual, Volume 1 and AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating System. If an application unmasks exceptions using either FXRSTOR or LDMXCSR without the required OS support being enabled, then an invalid opcode fault, instead of a SIMD floating-point exception, will be generated on the first faulting SIMD floating-point instruction. 11-11 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING 11.7.1. SIMD Floating-point Non-Numeric Exceptions • Exceptions during memory accesses: — Invalid opcode (#UD). — Stack exception (#SS). — General protection (#GP). — Page fault (#PF). — Alignment check (#AC), if alignment checking is enabled. • System exceptions: — Invalid Opcode (#UD), if the EM flag in control register CR0 is set, the CPUID.XMM bit is not set, or the CR4.OSFXSR* bit is not set, when a Streaming SIMD Extensions instruction is executed (see Section 10.1., “Emulation of the Streaming SIMD Extensions”). — Device not available (#NM), if a Streaming SIMD Extensions instruction is executed when the TS flag in control register CR0 is set. (See Section 10.6.1., “Using the TS Flag in Control Register CR0 to Control SIMD Floating-Point State Saving”.) • Other exceptions can occur indirectly due to the faulty execution of the exception handlers for the above exceptions. For example, if a stack-segment fault (#SS) occurs due to Streaming SIMD Extensions instructions, the interrupt gate for the stack-segment fault can direct the processor to invalid TSS, causing an invalid TSS exception (#TS) to be generated. Table 11-7 lists the causes for Interrupt 6 and Interrupt 7 with Streaming SIMD Extensions. Table 11-7. Streaming SIMD Extensions Faults CR0.EM 1 0 CR4.OSFXSR 0 1 CPUID.XMM 0 1 CR0.TS 1 EXCEPTION #UD Interrupt 6 #UD Interrupt 6 #UD Interrupt 6 #NM Interrupt 7 11-12 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING 11.7.2. SIMD Floating-point Numeric Exceptions There are six classes of numeric exception conditions that can occur while executing Streaming SIMD Extensions: • • • • • • Invalid operation (#I) Divide-by-zero (#Z) Denormal operand (#D) Numeric overflow (#O) Numeric underflow (#U) Inexact result (Precision) (#P) Invalid, Divide-by-zero and Denormal exceptions are pre-computation exceptions, i.e., they are detected before any arithmetic operation occurs. Underflow, Overflow and Precision exceptions are post-computation exceptions. When numeric exceptions occur, a processor supporting Streaming SIMD Extensions takes one of two possible courses of action: • • The processor can handle the exception by itself, producing the most reasonable result and allowing numeric program execution to continue undisturbed (i.e., masked exception response). A software exception handler can be invoked to handle the exception (i.e., unmasked exception response). Each of the six excepti...
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