This preview shows page 1. Sign up to view the full content.
Unformatted text preview: s* NOTE: * Using these encoding result in a general-protection exception (#GP) being generated. 9-19 MEMORY CACHE CONTROL Physical Memory
FFFFFFFFH Address ranges not mapped by an MTRR are set to a default type 8 variable ranges (from 4 KBytes to maximum size of physical memory) 64 fixed ranges (4 KBytes each) 16 fixed ranges (16 KBytes each) 8 fixed ranges (64-KBytes each) 256 KBytes 256 KBytes 512 KBytes 100000H FFFFFH C0000H BFFFFH 80000H 7FFFFH 0 Figure 9-3. Mapping Physical Memory With MTRRs 9.12.1. MTRR Feature Identification
The availability of the MTRR feature is model-specific. Software can determine if MTRRs are supported on a processor by executing the CPUID instruction and reading the state of the MTRR flag (bit 12) in the feature information register (EDX). If the MTRR flag is set (indicating that the processor implements MTRRs), additional information about MTRRs can be obtained from the 64-bit MTRRcap register. The MTRRcap register is a read-only MSR that can be read with the RDMSR instruction. Figure 9-4 shows the contents of the MTRRcap register. The functions of the flags and field in this register are as follows: VCNT (variable range registers count) field, bits 0 through 7 Indicates the number of variable ranges implemented on the processor. The P6 family processors have eight pairs of MTRRs for setting up eight variable ranges. 9-20 MEMORY CACHE CONTROL 63 11 10 9 8 7 0 Reserved WC—Write-combining memory type supported FIX—Fixed range registers supported VCNT—Number of variable range registers Reserved W C F I X VCNT Figure 9-4. MTRRcap Register FIX (fixed range registers supported) flag, bit 8 Fixed range MTRRs (MTRRfix64K_00000 through MTRRfix4K_0F8000) are supported when set; no fixed range registers are supported when clear. WC (write combining) flag, bit 10 The write-combining (WC) memory type is supported when set; the WC type is not supported when clear. Bit 9 and bits 11 through 63 in the MTRRcap register are reserved. If software attempts to write to the MTRRcap registers, a general-protection exception (#GP) is generated. For the P6 family processors, the MTRRcap register always contains the value 508H. 9.12.2. Setting Memory Ranges with MTRRs
The memory ranges and the types of memory specified in each range are set by three groups of registers: the MTRRdefType register, the fixed-range MTRRs, and the variable range MTRRs. These registers can be read and written to using the RDMSR and WRMSR instructions, respectively. The MTRRcap register indicates the availability of these registers on the processor. For more information, see Section 9.12.1., “MTRR Feature Identification”. 126.96.36.199. MTRRDEFTYPE REGISTER The MTRRdefType register (see Figure 9-4) sets the default properties of the regions of physical memory that are not encompassed by MTRRs. For more information, see Section 9.4., “Cache Control Protocol”. The functions of the flags and field in this register are as follows: Type field, bits 0 through 7 Indicates the default memory type used for those physical memory address ranges that do not have a memory type specified for them by an MTRR. See Table 9-6 for the encoding of this field. If the MTRRs are disabled, this field defines the memory type for all of physical memory. The legal values for this field are 0, 1, 4, 5, and 6. All other values result in a general-protection exception (#GP) being generated. 9-21 MEMORY CACHE CONTROL Intel recommends the use of the UC (uncached) memory type for all physical memory addresses where memory does not exist. To assign the UC type to nonexistent memory locations, it can either be specified as the default type in the Type field or be explicitly assigned with the fixed and variable MTRRs. 63 12 11 10 9 8 7 0 Reserved E—MTRR enable/disable FE—Fixed-range MTRRs enable/disable Type—Default memory type Reserved F EE Type Figure 9-5. MTRRdefType Register FE (fixed MTRRs enabled) flag, bit 10 Fixed-range MTRRs are enabled when set; fixed-range MTRRs are disabled when clear. When the fixed-range MTRRs are enabled, they take priority over the variable-range MTRRs when overlaps in ranges occur. If the fixed-range MTRRs are disabled, the variable-range MTRRs can still be used and can map the range ordinarily covered by the fixed-range MTRRs. E (MTRRs enabled) flag, bit 11 MTRRs are enabled when set; all MTRRs are disabled when clear, and the UC memory type is applied to all of physical memory. When this flag is set, the FE flag can disable the fixed-range MTRRs; when the flag is clear, the FE flag has no affect. When the E flag is set, the type specified in the default memory type field is used for areas of memory not already mapped by either a fixed or variable MTRR. Bits 8 and 9, and bits 12 through 63, in the MTRRdefType register are reserved; the processor generates a general-protection exception (#GP) if software attempts to write nonzero values to them. 188.8.131.52. FIXED RANGE MTRRS The fixed memory ranges are mapped with 8 fixed-range registers of 64 bits each. Each of these registers is divided into 8-bit fields that are used to specify...
View Full Document
This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10