IntelSoftwareDevelopersManual

G p d a c w p s dtsw available for system programmers

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Unformatted text preview: extension is being used. 3-23 PROTECTED-MODE MEMORY MANAGEMENT Page-Directory Entry (4-KByte Page Table) 31 Page-Table Base Address 12 11 9876543210 PPUR Avail. G P 0 A C W / / P S DTSW Available for system programmer’s use Global page (Ignored) Page size (0 indicates 4 KBytes) Reserved (set to 0) Accessed Cache disabled Write-through User/Supervisor Read/Write Present Page-Table Entry (4-KByte Page) 31 Page Base Address 12 11 9876543210 PPUR G 0DA CW/ / P DTSW Avail. Available for system programmer’s use Global page Reserved (set to 0) Dirty Accessed Cache disabled Write-through User/Supervisor Read/Write Present Figure 3-14. Format of Page-Directory and Page-Table Entries for 4-KByte Pages and 32-Bit Physical Addresses 3-24 PROTECTED-MODE MEMORY MANAGEMENT Page-Directory Entry (4-MByte Page) 31 Page Base Address 22 21 Reserved 12 11 9876543210 PPUR Avail. G P D A C W / / P S DTSW Available for system programmer’s use Global page Page size (1 indicates 4 MBytes) Dirty Accessed Cache disabled Write-through User/Supervisor Read/Write Present Figure 3-15. Format of Page-Directory Entries for 4-MByte Pages and 32-Bit Addresses The functions of the flags and fields in the entries in Figures 3-14 and 3-15 are as follows: Page base address, bits 12 through 32 (Page-table entries for 4-KByte pages.) Specifies the physical address of the first byte of a 4-KByte page. The bits in this field are interpreted as the 20 mostsignificant bits of the physical address, which forces pages to be aligned on 4-KByte boundaries. (Page-directory entries for 4-KByte page tables.) Specifies the physical address of the first byte of a page table. The bits in this field are interpreted as the 20 most-significant bits of the physical address, which forces page tables to be aligned on 4-KByte boundaries. (Page-directory entries for 4-MByte pages.) Specifies the physical address of the first byte of a 4-MByte page. Only bits 22 through 31 of this field are used (and bits 12 through 21 are reserved and must be set to 0, for Intel Architecture processors through the Pentium® II processor). The base address bits are interpreted as the 10 most-significant bits of the physical address, which forces 4MByte pages to be aligned on 4-MByte boundaries. Present (P) flag, bit 0 Indicates whether the page or page table being pointed to by the entry is currently loaded in physical memory. When the flag is set, the page is in physical memory and address translation is carried out. When the flag is clear, the page is not in memory and, if the processor attempts to access the page, it generates a page-fault exception (#PF). The processor does not set or clear this flag; it is up to the operating system or executive to maintain the state of the flag. 3-25 PROTECTED-MODE MEMORY MANAGEMENT The bit must be set to 1 whenever extended physical addressing mode is enabled. If the processor generates a page-fault exception, the operating system must carry out the following operations in the order below: 1. 2. Copy the page from disk storage into physical memory, if needed. Load the page address into the page-table or page-directory entry and set its present flag. Other bits, such as the dirty and accessed flags, may also be set at this time. Invalidate the current page-table entry in the TLB (refer to Section 3.7., “Translation Lookaside Buffers (TLBs)” for a discussion of TLBs and how to invalidate them). Return from the page-fault handler to restart the interrupted program or task. 3. 4. Read/write (R/W) flag, bit 1 Specifies the read-write privileges for a page or group of pages (in the case of a page-directory entry that points to a page table). When this flag is clear, the page is read only; when the flag is set, the page can be read and written into. This flag interacts with the U/S flag and the WP flag in register CR0. Refer to Section 4.11., “Page-Level Protection” and Table 4-2 in Chapter 4, Protection for a detailed discussion of the use of these flags. User/supervisor (U/S) flag, bit 2 Specifies the user-supervisor privileges for a page or group of pages (in the case of a page-directory entry that points to a page table). When this flag is clear, the page is assigned the supervisor privilege level; when the flag is set, the page is assigned the user privilege level. This flag interacts with the R/W flag and the WP flag in register CR0. Refer to Section 4.11., “Page-Level Protection” and Table 4-2 in Chapter 4, Protection for a detail discussion of the use of these flags. Page-level write-through (PWT) flag, bit 3 Controls the write-through or write-back caching policy of individual pages or page tables. When the PWT flag is set, write-through caching is enabled for the associated page or page table; when the flag is clear, write-back caching is enabled for the associated page or page table. The processor ignores this flag if the CD (cache disable) flag in CR0 is set. Refer to Section 9.5., “Cache Control”, in Chapter 9, Memory Cache Control, for more information about the use of this flag. Refer to Sec...
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