IntelSoftwareDevelopersManual

G flag only available in p6 family processors 2 if 36

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Unformatted text preview: rs? A write to this line … M (Modified) Yes …out of date No …does not go to bus E (Exclusive) Yes …valid No …does not go to bus S (Shared) Yes …valid Maybe …causes the processor to gain exclusive ownership of the line No — Maybe …goes directly to bus I (Invalid) 9.5. CACHE CONTROL The current Intel Architecture provides the following cache-control mechanisms for use in enabling caching and/or restricting caching to various pages or regions in memory (see Figure 9-2): • CD flag, bit 30 of control register CR0—Controls caching of system memory locations. For more information, see Section 2.5., “Control Registers”, in Chapter 2, System Architecture Overview. If the CD flag is clear, caching is enabled for the whole of system memory, but may be restricted for individual pages or regions of memory by other cachecontrol mechanisms. When the CD flag is set, caching is restricted in the L1 and L2 caches for the P6 family processors and prevented for the Pentium ® and Intel486™ processors (see note below). With the CD flag set, however, the caches will still respond to snoop traffic. Caches should be explicitly flushed to insure memory coherency. For highest processor performance, both the CD and the NW flags in control register CR0 should be cleared. Table 9-4 shows the interaction of the CD and NW flags. 9-9 MEMORY CACHE CONTROL NOTE The effect of setting the CD flag is somewhat different for the P6 family, Pentium®, and Intel486™ processors (see Table 9-4). To insure memory coherency after the CD flag is set, the caches should be explicitly flushed. For more information, see Section 9.5.2., “Preventing Caching”. Setting the CD flag for the P6 family processors modifies cache line fill and update behaviour. Also for the P6 family processors, setting the CD flag does not force strict ordering of memory accesses unless the MTRRs are disabled and/or all memory is referenced as uncached. For more information, see Section 7.2.4., “Strengthening or Weakening the Memory Ordering Model”, in Chapter 7, Multiple-Processor Management. CR4 P G E CR3 PP CW DT Enables global pages designated with G flag Physical Memory FFFFFFFFH2 Control caching of page directory Page-Directory or Page-Table Entry PP G1 C W DT CR0 CN DW MTRRs3 MTRRs control caching of selected regions of physical memory Memory Types Allowed: —Uncacheable (UC) —Write-Protected (WP) —Write-Combining (WC) —Write-Through (WT) —Write-Back (WB) CD and NW Flags control overall caching of system memory PCD and PWT flags control page-level caching G flag controls pagelevel flushing of TLBs 0 Write Buffer TLBs 1. G flag only available in P6 family processors. 2. If 36-bit physical addressing is being used, the maximum physical address size is FFFFFFFFFH. 3. MTRRs available only in P6 family processors; similar control available in Pentium® processor with KEN# and WB/WT# pins, and in Intel486™ processor. Figure 9-2. Cache-Control Mechanisms Available in the Intel Architecture Processors 9-10 MEMORY CACHE CONTROL Table 9-4. Cache Operating Modes CD 0 NW 0 Caching and Read/Write Policy Normal highest performance cache operation. - Read hits access the cache; read misses may cause replacement. - Write hits update the cache. - (Pentium® and P6 family processors.) Only writes to shared lines and write misses update system memory. - (P6 family processors.) Write misses cause cache line fills; write hits can change shared lines to exclusive under control of the MTRRs - (Pentium® processor.) Write misses do not cause cache line fills; write hits can change shared lines to exclusive under control of WB/WT#. - (Intel486™ processor.) All writes update system memory; write misses do not cause cache line fills. - Invalidation is allowed. - External snoop traffic is supported. Invalid setting. A general-protection exception (#GP) with an error code of 0 is generated. Memory coherency is maintained. - Read hits access the cache; read misses do not cause replacement. - Write hits update the cache. - (Pentium® and P6 family processors.) Only writes to shared lines and write misses update system memory. - (Intel486™ processor.) All writes update system memory - (Pentium® processor.) Write hits can change shared lines to exclusive under control of the WB/WT#. - (P6 family processors.) Strict memory ordering is not enforced unless the MTRRs are disabled and/or all memory is referenced as uncached. For more information, see Section 7.2.4., “Strengthening or Weakening the Memory Ordering Model”. - Invalidation is allowed. - External snoop traffic is supported. Memory coherency is not maintained. This is the state of the processor after a power up or reset. - Read hits access the cache; read misses do not cause replacement. - Write hits update the cache. - (Pentium® and P6 family processors.) Write hits change exclusive lines to modified. - (Pentium® and P6 family processors.) Shared lines remain shared after write hit. - Write misses access memory. - (P6 family...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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