However during a hardware reset the segment selector

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Unformatted text preview: TION Paging disabled: 0 Caching disabled: 1 Not write-through disabled: 1 Alignment check disabled: 0 Write-protect disabled: 0 31 30 29 28 19 18 17 16 15 6543210 PCN GDW A M W P N T EMP 1 E SMPE External FPU error reporting: 0 (Not used): 1 No task switch: 0 FPU instructions not trapped: 0 WAIT/FWAIT instructions not trapped: 0 Real-address mode: 0 Reserved Figure 8-1. Contents of CR0 Register after Reset 8.1.3. Model and Stepping Information Following a hardware reset, the EDX register contains component identification and revision information (refer to Figure 8-2). The device ID field is set to the value 6H, 5H, 4H, or 3H to indicate a Pentium® Pro, Pentium®, Intel486™, or Intel386™ processor, respectively. Different values may be returned for the various members of these Intel Architecture families. For example the Intel386™ SX processor returns 23H in the device ID field. Binary object code can be made compatible with other Intel processors by using this number to select the correct initialization software. 31 14 13 12 11 87 43 0 EDX Family Model Stepping ID Processor Type Family (0110B for the Pentium® Pro Processor Family) Model (Beginning with 0001B) Reserved Figure 8-2. Processor Type and Signature in the EDX Register after Reset 8-5 PROCESSOR MANAGEMENT AND INITIALIZATION The stepping ID field contains a unique identifier for the processor’s stepping ID or revision level. The upper word of EDX is reserved following reset. 8.1.4. First Instruction Executed The first instruction that is fetched and executed following a hardware reset is located at physical address FFFFFFF0H. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the software-initialization code must be located at this address. The address FFFFFFF0H is beyond the 1-MByte addressable range of the processor while in real-address mode. The processor is initialized to this starting address as follows. The CS register has two parts: the visible segment selector part and the hidden base address part. In realaddress mode, the base address is normally formed by shifting the 16-bit segment selector value 4 bits to the left to produce a 20-bit base address. However, during a hardware reset, the segment selector in the CS register is loaded with F000H and the base address is loaded with FFFF0000H. The starting address is thus formed by adding the base address to the value in the EIP register (that is, FFFF0000 + FFF0H = FFFFFFF0H). The first time the CS register is loaded with a new value after a hardware reset, the processor will follow the normal rule for address translation in real-address mode (that is, [CS base address = CS segment selector * 16]). To insure that the base address in the CS register remains unchanged until the EPROM based software-initialization code is completed, the code must not contain a far jump or far call or allow an interrupt to occur (which would cause the CS selector value to be changed). 8.2. FPU INITIALIZATION Software-initialization code can determine the whether the processor contains or is attached to an FPU by using the CPUID instruction. The code must then initialize the FPU and set flags in control register CR0 to reflect the state of the FPU environment. A hardware reset places the Pentium® processor FPU in the state shown in Table 8-1. This state is different from the state the processor is placed in when executing an FINIT or FNINIT instruction (also shown in Table 8-1). If the FPU is to be used, the software-initialization code should execute an FINIT/FNINIT instruction following a hardware reset. These instructions, tag all data registers as empty, clear all the exception masks, set the TOP-of-stack value to 0, and select the default rounding and precision controls setting (round to nearest and 64-bit precision). If the processor is reset by asserting the INIT# pin, the FPU state is not changed. 8.2.1. Configuring the FPU Environment Initialization code must load the appropriate values into the MP, EM, and NE flags of control register CR0. These bits are cleared on hardware reset of the processor. Figure 8-2 shows the suggested settings for these flags, depending on the Intel Architecture processor being initial- 8-6 PROCESSOR MANAGEMENT AND INITIALIZATION ized. Initialization code can test for the type of processor present before setting or clearing these flags. Table 8-2. Recommended Settings of EM and MP Flags on Intel Architecture Processors EM 1 0 MP 0 1 NE 1 1 or 0* Intel Architecture Processor Intel486™ SX, Intel386™ DX, and Intel386™ SX processors only, without the presence of a math coprocessor. Pentium® Pro, Pentium®, Intel486™ DX, and Intel 487 SX processors, and also Intel386™ DX and Intel386™ SX processors when a companion math coprocessor is present. NOTE: * The setting of the NE flag depends on the operating system being used. The EM flag determines whether floating-point instructions are executed by the FPU (EM is cleared) or generate a device-not-available exception (#NM) so that an exception handler can emulate...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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