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Unformatted text preview: debug-exception conditions has been detected. Whether the exception is a fault or a trap depends on the condition, as shown below:
Exception Condition Instruction fetch breakpoint Data read or write breakpoint I/O read or write breakpoint General detect condition (in conjunction with in-circuit emulation) Single-step Task-switch Execution of INT 1 instruction Fault Trap Trap Fault Trap Trap Trap Exception Class Refer to Chapter 15, Debugging and Performance Monitoring, for detailed information about the debug exceptions. Exception Error Code None. An exception handler can examine the debug registers to determine which condition caused the exception. Saved Instruction Pointer Fault—Saved contents of CS and EIP registers point to the instruction that generated the exception. Trap—Saved contents of CS and EIP registers point to the instruction following the instruction that generated the exception. Program State Change Fault—A program-state change does not accompany the debug exception, because the exception occurs before the faulting instruction is executed. The program can resume normal execution upon returning from the debug exception handler Trap—A program-state change does accompany the debug exception, because the instruction or task switch being executed is allowed to complete before the exception is generated. However, the new state of the program is not corrupted and execution of the program can continue reliably. 5-23 INTERRUPT AND EXCEPTION HANDLING Interrupt 2—NMI Interrupt
Exception Class Description The nonmaskable interrupt (NMI) is generated externally by asserting the processor’s NMI pin or through an NMI request set by the I/O APIC to the local APIC on the APIC serial bus. This interrupt causes the NMI interrupt handler to be called. Exception Error Code Not applicable. Saved Instruction Pointer The processor always takes an NMI interrupt on an instruction boundary. The saved contents of CS and EIP registers point to the next instruction to be executed at the point the interrupt is taken. Refer to Section 5.4., “Program or Task Restart” for more information about when the processor takes NMI interrupts. Program State Change The instruction executing when an NMI interrupt is received is completed before the NMI is generated. A program or task can thus be restarted upon returning from an interrupt handler without loss of continuity, provided the interrupt handler saves the state of the processor before handling the interrupt and restores the processor’s state prior to a return. Not applicable. 5-24 INTERRUPT AND EXCEPTION HANDLING Interrupt 3—Breakpoint Exception (#BP)
Exception Class Description Indicates that a breakpoint instruction (INT 3) was executed, causing a breakpoint trap to be generated. Typically, a debugger sets a breakpoint by replacing the first opcode byte of an instruction with the opcode for the INT 3 instruction. (The INT 3 instruction is one byte long, which makes it easy to replace an opcode in a code segment in RAM with the breakpoint opcode.) The operating system or a debugging tool can use a data segment mapped to the same physical address space as the code segment to place an INT 3 instruction in places where it is desired to call the debugger. With the P6 family, Pentium®, Intel486™, and Intel386™ processors, it is more convenient to set breakpoints with the debug registers. (Refer to Section 15.3.2., “Breakpoint Exception (#BP)—Interrupt Vector 3”, in Chapter 15, Debugging and Performance Monitoring, for information about the breakpoint exception.) If more breakpoints are needed beyond what the debug registers allow, the INT 3 instruction can be used. The breakpoint (#BP) exception can also be generated by executing the INT n instruction with an operand of 3. The action of this instruction (INT 3) is slightly different than that of the INT 3 instruction (refer to “INTn/INTO/INT3—Call to Interrupt Procedure” in Chapter 3 of the Intel Architecture Software Developer’s Manual, Volume 2). Exception Error Code None. Saved Instruction Pointer Saved contents of CS and EIP registers point to the instruction following the INT 3 instruction. Program State Change Even though the EIP points to the instruction following the breakpoint instruction, the state of the program is essentially unchanged because the INT 3 instruction does not affect any register or memory locations. The debugger can thus resume the suspended program by replacing the INT 3 instruction that caused the breakpoint with the original opcode and decrementing the saved contents of the EIP register. Upon returning from the debugger, program execution resumes with the replaced instruction. Trap. 5-25 INTERRUPT AND EXCEPTION HANDLING Interrupt 4—Overflow Exception (#OF)
Exception Class Description Indicates that an overflow trap occurred when an INTO instruction was executed. The INTO instruction checks the state of the OF flag in the EFLAGS register. If the OF flag is set, an overflow trap is generated. Some arithmetic instructions (such as the ADD and SU...
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- Spring '10