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Unformatted text preview: DX ECX EAX EFLAGS EIP CR3 (PDBR) ESP2 ESP1 ESP0 Reserved bits. Set to 0. Figure 6-2. 32-Bit Task-State Segment (TSS) 6-5 TASK MANAGEMENT CR3 control register field Contains the base physical address of the page directory to be used by the task. Control register CR3 is also known as the page-directory base register (PDBR). Privilege level-0, -1, and -2 stack pointer fields These stack pointers consist of a logical address made up of the segment selector for the stack segment (SS0, SS1, and SS2) and an offset into the stack (ESP0, ESP1, and ESP2). Note that the values in these fields are static for a particular task; whereas, the SS and ESP values will change if stack switching occurs within the task. T (debug trap) flag (byte 100, bit 0) When set, the T flag causes the processor to raise a debug exception when a task switch to this task occurs (refer to Section, “Task-Switch Exception Condition”, in Chapter 15, Debugging and Performance Monitoring). I/O map base address field Contains a 16-bit offset from the base of the TSS to the I/O permission bit map and interrupt redirection bitmap. When present, these maps are stored in the TSS at higher addresses. The I/O map base address points to the beginning of the I/O permission bit map and the end of the interrupt redirection bit map. Refer to Chapter 9, Input/Output, in the Intel Architecture Software Developer’s Manual, Volume 1, for more information about the I/O permission bit map. Refer to Section 16.3., “Interrupt and Exception Handling in Virtual8086 Mode” in Chapter 16, 8086 Emulation for a detailed description of the interrupt redirection bit map. If paging is used, care should be taken to avoid placing a page boundary within the part of the TSS that the processor reads during a task switch (the first 104 bytes). If a page boundary is placed within this part of the TSS, the pages on either side of the boundary must be present at the same time and contiguous in physical memory. The reason for this restriction is that when accessing a TSS during a task switch, the processor reads and writes into the first 104 bytes of each TSS from contiguous physical addresses beginning with the physical address of the first byte of the TSS. It may not perform address translations at a page boundary if one occurs within this area. So, after the TSS access begins, if a part of the 104 bytes is not both present and physically contiguous, the processor will access incorrect TSS information, without generating a page-fault exception. The reading of this incorrect information will generally lead to an unrecoverable exception later in the task switch process. Also, if paging is used, the pages corresponding to the previous task’s TSS, the current task’s TSS, and the descriptor table entries for each should be marked as read/write. The task switch will be carried out faster if the pages containing these structures are also present in memory before the task switch is initiated. 6.2.2. TSS Descriptor The TSS, like all other segments, is defined by a segment descriptor. Figure 6-3 shows the format of a TSS descriptor. TSS descriptors may only be placed in the GDT; they cannot be placed in an LDT or the IDT. An attempt to access a TSS using a segment selector with its TI 6-6 TASK MANAGEMENT flag set (which indicates the current LDT) causes a general-protection exception (#GP) to be generated. A general-protection exception is also generated if an attempt is made to load a segment selector for a TSS into a segment register. The busy flag (B) in the type field indicates whether the task is busy. A busy task is currently running or is suspended. A type field with a value of 1001B indicates an inactive task; a value of 1011B indicates a busy task. Tasks are not recursive. The processor uses the busy flag to detect an attempt to call a task whose execution has been interrupted. To insure that there is only one busy flag is associated with a task, each TSS should have only one TSS descriptor that points to it. TSS Descriptor 31 24 23 22 21 20 19 16 15 14 13 12 11 87 0 A G00V L D P L Base 31:24 Limit 19:16 P Type 010B1 Base 23:16 4 0 31 16 15 Base Address 15:00 Segment Limit 15:00 0 AVL B BASE DPL G LIMIT P TYPE Available for use by system software Busy flag Segment Base Address Descriptor Privilege Level Granularity Segment Limit Segment Present Segment Type Figure 6-3. TSS Descriptor The base, limit, and DPL fields and the granularity and present flags have functions similar to their use in data-segment descriptors (refer to Section 3.4.3., “Segment Descriptors” in Chapter 3, Protected-Mode Memory Management). The limit field must have a value equal to or greater than 67H (for a 32-bit TSS), one byte less than the minimum size of a TSS. Attempting to switch to a task whose TSS descriptor has a limit less than 67H generates an invalid-TSS exception (#TS). A larger limit is required if an I/O permission bit map is included in the TSS. An even larger limit would be required if the operating system stores additional data in the TSS. The processor does not check fo...
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