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Unformatted text preview: o the page. By using the WP flag and marking the shared pages as readonly, the supervisor can detect an attempt to write to a user-level page, and can copy the page at that time. 4.11.4. Combining Protection of Both Levels of Page Tables For any one page, the protection attributes of its page-directory entry (first-level page table) may differ from those of its page-table entry (second-level page table). The processor checks the protection for a page in both its page-directory and the page-table entries. Table 4-2 shows the protection provided by the possible combinations of protection attributes when the WP flag is clear. 4.11.5. Overrides to Page Protection The following types of memory accesses are checked as if they are privilege-level 0 accesses, regardless of the CPL at which the processor is currently operating: • • Access to segment descriptors in the GDT, LDT, or IDT. Access to an inner-privilege-level stack during an inter-privilege-level call or a call to in exception or interrupt handler, when a change of privilege level occurs. 4-32 PROTECTION 4.12. COMBINING PAGE AND SEGMENT PROTECTION
When paging is enabled, the processor evaluates segment protection first, then evaluates page protection. If the processor detects a protection violation at either the segment level or the page level, the memory access is not carried out and an exception is generated. If an exception is generated by segmentation, no paging exception is generated. Page-level protections cannot be used to override segment-level protection. For example, a code segment is by definition not writable. If a code segment is paged, setting the R/W flag for the pages to read-write does not make the pages writable. Attempts to write into the pages will be blocked by segment-level protection checks. Page-level protection can be used to enhance segment-level protection. For example, if a large read-write data segment is paged, the page-protection mechanism can be used to write-protect individual pages.
Table 4-2. Combined Page-Directory and Page-Table Protection
Page-Directory Entry Privilege User User User User User User User User Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor NOTE: * If the WP flag of CR0 is set, the access type is determined by the R/W flags of the page-directory and page-table entries. Access Type Read-Only Read-Only Read-Write Read-Write Read-Only Read-Only Read-Write Read-Write Read-Only Read-Only Read-Write Read-Write Read-Only Read-Only Read-Write Read-Write Page-Table Entry Privilege User User User User Supervisor Supervisor Supervisor Supervisor User User User User Supervisor Supervisor Supervisor Supervisor Access Type Read-Only Read-Write Read-Only Read-Write Read-Only Read-Write Read-Only Read-Write Read-Only Read-Write Read-Only Read-Write Read-Only Read-Write Read-Only Read-Write Combined Effect Privilege User User User User Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Supervisor Access Type Read-Only Read-Only Read-Only Read/Write Read/Write* Read/Write* Read/Write* Read/Write Read/Write* Read/Write* Read/Write* Read/Write Read/Write* Read/Write* Read/Write* Read/Write 4-33 PROTECTION 4-34 5
Interrupt and Exception Handling INTERRUPT AND EXCEPTION HANDLING CHAPTER 5 INTERRUPT AND EXCEPTION HANDLING
This chapter describes the processor’s interrupt and exception-handling mechanism, when operating in protected mode. Most of the information provided here also applies to the interrupt and exception mechanism used in real-address or virtual-8086 mode. Refer to Chapter 16, 8086 Emulation for a description of the differences in the interrupt and exception mechanism for realaddress and virtual-8086 mode. 5.1. INTERRUPT AND EXCEPTION OVERVIEW Interrupts and exceptions are forced transfers of execution from the currently running program or task to a special procedure or task called a handler. Interrupts typically occur at random times during the execution of a program, in response to signals from hardware. They are used to handle events external to the processor, such as requests to service peripheral devices. Software can also generate interrupts by executing the INT n instruction. Exceptions occur when the processor detects an error condition while executing an instruction, such as division by zero. The processor detects a variety of error conditions including protection violations, page faults, and internal machine faults. The machine-check architecture of the P6 family and Pentium® processors also permits a machine-check exception to be generated when internal hardware errors and bus errors are detected. The processor’s interrupt and exception-handling mechanism allows interrupts and exceptions to be handled transparently to application programs and the operating system or executive. When an interrupt is received or an exception is detected, the currently running procedure or task is automatically suspended while the processor executes...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10