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Unformatted text preview: pplication TSS in GDT entry 10 Initialization code size must be less than 64K and resides at upper most 64K of the 4GB memory space. IDT location RAM start Location of the application TSS in the GDT EPROM size and location TSS_INDEX EQU 10 TABLE GDT( ENTRY=( 10: PROTECTED_MODE_TA SK)) SEGMENT startup.code (base= 0FFFF0000H) ...memory (RANGE( ROM_AREA = ROM(x..y)) size and location of the initialization code 8.10. P6 FAMILY MICROCODE UPDATE FEATURE
P6 family processors have the capability to correct specific errata through the loading of an Intel-supplied data block. This data block is referred to as a microcode update. This chapter describes the underlying mechanisms the BIOS needs to provide in order to utilize this feature during system initialization. It also describes a specification that provides for incorporating future releases of the microcode update into a system BIOS. Intel considers the combination of a particular silicon revision and the microcode update as the equivalent stepping of the processor. Intel does not validate processors without the microcode update loaded. Intel completes a full-stepping level validation and testing for new releases of microcode updates. A microcode update is used to correct specific errata in the processor. The BIOS, which incorporates an update loader, is responsible for loading the appropriate update on all processors during system initialization (refer to Figure 8-7). There are effectively two steps to this process. The first is to incorporate the necessary microcode updates into the BIOS, the second is to actually load the appropriate microcode update into the processor. 8-31 PROCESSOR MANAGEMENT AND INITIALIZATION UPDATE LOADER Update Blocks New Update BIOS P6 Family CPU Figure 8-7. Integrating Processor Specific Updates 8.10.1. Microcode Update
A microcode update consists of an Intel-supplied binary that contains a descriptive header and data. No executable code resides within the update. This section describes the update and the structure of its data format. Each microcode update is tailored for a particular stepping of a P6 family processor. It is designed such that a mismatch between a stepping of the processor and the update will result in a failure to load. Thus, a given microcode update is associated with a particular type, family, model, and stepping of the processor as returned by the CPUID instruction. In addition, the intended processor platform type must be determined to properly target the microcode update. The intended processor platform type is determined by reading a model-specific register MSR (17h) (refer to Table 8-6) within the P6 family processor. This is a 64-bit register that may be read using the RDMSR instruction (refer to Section 3.2., “Instruction Reference” Chapter 3, Instruction Set Reference, Volume 1 of the Programmer’s Reference Manual). The three platform ID bits, when read as a binary coded decimal (BCD) number indicate the bit position in the microcode update header’s, Processor Flags field, that is associated with the installed processor. 8-32 PROCESSOR MANAGEMENT AND INITIALIZATION Register Name:BBL_CR_OVRD MSR Address:017h Access:Read Only BBL_CR_OVRD is a 64-bit register accessed only when referenced as a Qword through a RDMSR instruction. Table 8-6. P6 Family Processor MSR Register Components
Bit 63:53 52:50 Reserved Platform ID bits (RO). The field gives information concerning the intended platform for the processor. 52 51 50 0 0 0 Processor Flag 0 (See Processor Flags in Microcode Update Header) 0 0 1 Processor Flag 1 0 1 0 Processor Flag 2 0 1 1 Processor Flag 3 1 0 0 Processor Flag 4 1 0 1 Processor Flag 5 1 1 0 Processor Flag 6 1 1 1 Processor Flag 7 Reserved Descriptions 49:0 The microcode update is a data block that is exactly 2048 bytes in length. The initial 48 bytes of the update contain a header with information used to identify the update. The update header and its reserved fields are interpreted by software based upon the header version. The initial version of the header is 00000001h. An encoding scheme also guards against tampering of the update data and provides a means for determining the authenticity of any given update. Table 8-7 defines each of the fields and Figure 8-8 shows the format of the microcode update data block. 8-33 PROCESSOR MANAGEMENT AND INITIALIZATION Table 8-7. Microcode Update Encoding Format
Field Name Header Version Update Revision Offset (in bytes) 0 4 Length (in bytes) 4 4 Description Version number of the update header. Unique version number for the update, the basis for the update signature provided by the processor to indicate the current update functioning within the processor. Used by the BIOS to authenticate the update and verify that it is loaded successfully by the processor. The value in this field cannot be used for processor stepping identification alone. Date of the update creation in binary format: mmddyyyy (e.g. 07/18/98 is 07181998h). Date Processor 8 12 4 4 Processor type, family, model, and stepping of processor that requires this particular update revision (e.g., 00000650h). Each microcode update is designed specifically for a given processor type, family, model, and stepping of processor. The BIOS uses the Processor field in conjunction with the CPUID instruction to determine whether or not an update is approp...
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