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Unformatted text preview: local APIC detects a check sum error for a message that was sent by it. Set when the local APIC detects a check sum error for a message that was received by it. Set when the local APIC detects that a message it sent was not accepted by any APIC on the bus. Set when the local APIC detects that the message it received was not accepted by any APIC on the bus, including itself. Set when the local APIC detects an illegal vector in the message that it is sending on the bus. Set when the local APIC detects an illegal vector in the message it received, including an illegal vector code in the local vector table interrupts and self-interrupts from ICR. Set when the processor is trying to access a register that is not implemented in the P6 family processors’ local APIC register address space; that is, within FEE00000H (the APICBase MSR) through FEE003FFH (the APICBase MSR plus 4K Bytes). Illegal Reg. Address (P6 Family Processors Only) 7.5.18. Timer
The local APIC unit contains a 32-bit programmable timer for use by the local processor. This timer is configured through the timer register in the local vector table (refer to Figure 7-8). The time base is derived from the processor’s bus clock, divided by a value specified in the divide configuration register (refer to Figure 7-17). After reset, the timer is initialized to zero. The timer supports one-shot and periodic modes. The timer can be configured to interrupt the local processor with an arbitrary vector. 31 4 3210 Reserved Address: FEE0 03E0H Value after reset: 0H 0 Divide Value (bits 0, 1 and 3) 000: Divide by 2 001: Divide by 4 010: Divide by 8 011: Divide by 16 100: Divide by 32 101: Divide by 64 110: Divide by 128 111: Divide by 1 Figure 7-17. Divide Configuration Register 7-43 MULTIPLE-PROCESSOR MANAGEMENT The timer is started by programming its initial-count register, refer to Figure 7-18. The initial count value is copied into the current-count register and count-down is begun. After the timer reaches zero in one-shot mode, an interrupt is generated and the timer remains at its 0 value until reprogrammed. In periodic mode, the current-count register is automatically reloaded from the initial-count register when the count reaches 0 and the count-down is repeated. If during the count-down process the initial-count register is set, the counting will restart and the new value will be used. The initial-count register is read-write by software, while the current-count register is read only.
31 0 Initial Count Current Count Address: Initial Count FEE0 0380H Current Count FEE0 0390H Value after reset: 0H Figure 7-18. Initial Count and Current Count Registers 7.5.19. Software Visible Differences Between the Local APIC and the 82489DX
The following local APIC features differ in their definitions from the 82489DX features: • When the local APIC is disabled, its internal registers are not cleared. Instead, setting the mask bits in the local vector table to disable the local APIC merely causes it to cease accepting the bus messages except for INIT, SMI, NMI, and start-up. In the 82489DX, when the local unit is disabled by resetting the bit 8 of the spurious vector register, all the internal registers including the IRR, ISR and TMR are cleared and the mask bits in the local vector tables are set to logical ones. In the disabled mode, 82489DX local unit will accept only the reset deassert message. In the local APIC, NMI and INIT (except for INIT deassert) are always treated as edge triggered interrupts, even if programmed otherwise. In the 82489DX these interrupts are always level triggered. In the local APIC, interrupts generated through ICR messages are always treated as edge triggered (except INIT Deassert). In the 82489DX, the ICR can be used to generate either edge or level triggered interrupts. Logical Destination register the local APIC supports 8 bits, where it supports 32 bits for the 82489DX. APIC ID register is 4 bits wide for the local APIC and 8 bits wide for the 82489DX. The remote read delivery mode provided in the 82489DX is not supported in the Intel Architecture local APIC. • • • • • 7-44 MULTIPLE-PROCESSOR MANAGEMENT 7.5.20. Performance Related Differences between the Local APIC and the 82489DX
For the 82489DX, in the lowest priority mode, all the target local APICs specified by the destination field participate in the lowest priority arbitration. Only those local APICs which have free interrupt slots will participate in the lowest priority arbitration. 7.5.21. New Features Incorporated in the Pentium® and P6 Family Processors Local APIC
The local APIC in the Pentium® and P6 family processors have the following new features not found in the 82489DX. • • • • • The local APIC supports cluster addressing in logical destination mode. Focus processor checking can be enabled/disabled in the local APIC. Interrupt input signal polarity can be programmed in the local APIC. The local APIC supports SMI through the ICR and I/O redirection table. Th...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10