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Unformatted text preview: itch is about to occur and can save state prior to the task switch. The operating system can take the responsibility for automatically saving the MMX™/FPU state as part of the task switch process (using an FXSAVE/FSAVE instruction) and automatically restoring the MMX™/FPU state when a suspended task is resumed (using an FXRSTOR/FRSTOR instruction). Here, the MMX™/FPU state must be saved as part of the task state. This approach is appropriate for preemptive multitasking operating systems, where the application cannot know when it is going to be preempted and cannot prepare in advance for task switching. The operating system is responsible for saving and restoring the task and MMX™/FPU state when necessary. The operating system can take the responsibility for saving the MMX™/FPU state as part of the task switch process, but delay the saving of the MMX™/FPU state until an MMX™ or floating-point instruction is actually executed by the new task. Using this approach, the MMX™/FPU state is saved only if an MMX™ or floating-point instruction needs to be executed in the new task. (Refer to Section 10.4.1., “Using the TS Flag in Control Register CR0 to Control MMX™/FPU State Saving”, for more information on this MMX™/FPU state saving technique.) • • 10.4.1. Using the TS Flag in Control Register CR0 to Control MMX™/FPU State Saving
Saving the MMX™/FPU state using the FXSAVE/FSAVE instruction is a relatively high-overhead operation. If a task being switched to will not access the FPU (by executing an MMX™ or a floating-point instruction), this overhead can be avoided by not automatically saving the MMX™/FPU state on a task switch. 10-5 MMX™ TECHNOLOGY SYSTEM PROGRAMMING The TS flag in control register CR0 is provided to allow the operating system to delay saving the MMX™/FPU state until the FPU is actually accessed in the new task. When this flag is set, the processor monitors the instruction stream for MMX™ or floating-point instructions. When the processor detects an MMX™ or floating-point instruction, it raises a device-not-available exception (#NM) prior to executing the instruction. The device-not-available exception handler can then be used to save the MMX™/FPU state for the previous task (using an FXSAVE/FSAVE instruction) and load the MMX™/FPU state for the current task (using an FXRSTOR/FRSTOR instruction). If the task never encounters an MMX™ or floating-point instruction, the devicenot-available exception will not be raised and the MMX™/FPU state will not be saved unnecessarily. The TS flag can be set either explicitly (by executing a MOV instruction to control register CR0) or implicitly (using the processors native task switching mechanism). When the native task switching mechanism is used, the processor automatically sets the TS flag on a task switch. After the device-not-available handler has saved the MMX™/FPU state, it should execute the CLTS instruction to clear the TS flag in CR0. Figure 10-2 gives an example of an operating system that implements MMX™/FPU state saving using the TS flag. In this example, task A is the currently running task and task B is the task being switched to. Task A Application Operating System Task A MMX™/FPU State Save Area Operating System Task Switching Code Saves Task A MMX™/FPU State Device-Not-Available Exception Handler MMX™/FPU State Owner Task B CR0.TS=1 and Task B Floating-point or MMX™/FPU MMX™ Instruction State Save Area is encountered. Loads Task B MMX™/FPU State Figure 10-2. Example of MMX™/FPU State Saving During an Operating System-Controlled Task Switch The operating system maintains an MMX™/FPU save area for each task and defines a variable (MMX™/FPUStateOwner) that indicates which task “owns” the MMX™/FPU state. In this example, task A is the current MMX™/FPU state owner. On a task switch, the operating system task switching code must execute the following pseudocode to set the TS flag according to who is the current MMX™/FPU state owner. If the new task 10-6 MMX™ TECHNOLOGY SYSTEM PROGRAMMING (task B in this example) is not the current MMX™/FPU state owner, the TS flag is set to 1; otherwise, it is set to 0.
IF Task_Being_Switched_To ≠ MMX/FPUStateOwner THEN CR0.TS ← 1; ELSE CR0.TS ← 0; FI; If a new task attempts to use an MMX™ or floating-point instruction while the TS flag is set to 1, a device-not-available exception (#NM) is generated and the device-not-available exception handler executes the following pseudo-code.
CR0.TS ← 0; FSAVE “To MMX/FPU State Save Area for Current MMX/FPU State Owner”; FRSTOR “MMX/FPU State From Current Task’s MMX/FPU State Save Area”; MMX/FPUStateOwner ← Current_Task; This handler code performs the following tasks: • • • • Clears the TS flag. Saves the MMX™/FPU state in the state save area for the current MMX™/FPU state owner. Restores the MMX™/FPU state from the new task’s MMX™/FPU state save area. Updates the current MMX™/FPU state owner to be the current task. 10.5. EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX™ INSTRUCTIONS
MMX™ instructions do not generate floating-point exceptions, nor do they affect the processor’s status flags in the EFLAGS register or the FPU status word. The following exceptions can be generated duri...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10