Intel pentium pro processor specification update

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Unformatted text preview: P(0) Refer to Chapter 5, Interrupt and Exception Handling, for a list of exception mnemonics and their descriptions. 1-8 ABOUT THIS MANUAL 1.6. RELATED LITERATURE The following books contain additional material related to Intel processors: • • • • • • • • • • • • • • • • • • • • • Intel Pentium® II Processor Specification Update, Order Number 243337-010. Intel Pentium® Pro Processor Specification Update, Order Number 242689-031. Intel Pentium® Processor Specification Update, Order Number 242480. AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618006. AP-578, Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors, Order Number 243291. Pentium® Pro Processor Data Book, Order Number 242690. Pentium® Pro BIOS Writer’s Guide, Pentium® Processor Data Book, Order Number 241428. 82496 Cache Controller and 82491 Cache SRAM Data Book For Use With the Pentium® Processor, Order Number 241429. Intel486™ Microprocessor Data Book, Order Number 240440. Intel486™ SX CPU/Intel487™ SX Math Coprocessor Data Book , Order Number 240950. Intel486™ DX2 Microprocessor Data Book, Order Number 241245. Intel486™ Microprocessor Product Brief Book, Order Number 240459. Intel386™ Processor Hardware Reference Manual, Order Number 231732. Intel386™ Processor System Software Writer's Guide, Order Number 231499. Intel386™ High-Performance 32-Bit CHMOS Microprocessor with Integrated Memory Management, Order Number 231630. 376 Embedded Processor Programmer’s Reference Manual, Order Number 240314. 80387 DX User’s Manual Programmer’s Reference, Order Number 231917. 376 High-Performance 32-Bit Embedded Processor, Order Number 240182. Intel386™ SX Microprocessor, Order Number 240187. Intel Architecture Optimization Manual, Order Number 242816-002. 1-9 ABOUT THIS MANUAL 1-10 2 System Architecture Overview SYSTEM ARCHITECTURE OVERVIEW CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW The 32-bit members of the Intel Architecture family of processors provide extensive support for operating-system and system-development software. This support is part of the processor’s system-level architecture and includes features to assist in the following operations: • • • • • • • • Memory management Protection of software modules Multitasking Exception and interrupt handling Multiprocessing Cache management Hardware resource and power management Debugging and performance monitoring This chapter provides a brief overview of the processor’s system-level architecture; a detailed description of each part of this architecture given in the following chapters. This chapter also describes the system registers that are used to set up and control the processor at the system level and gives a brief overview of the processor’s system-level (operating system) instructions. Many of the system-level architectural features of the processor are used only by system programmers. Application programmers may need to read this chapter, and the following chapters which describe the use of these features, in order to understand the hardware facilities used by system programmers to create a reliable and secure environment for application programs. NOTE This overview and most of the subsequent chapters of this book focus on the “native” or protected-mode operation of the 32-bit Intel Architecture processors. As described in Chapter 8, Processor Management and Initialization, all Intel Architecture processors enter real-address mode following a power-up or reset. Software must then initiate a switch from real-address mode to protected mode. 2.1. OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE The Intel Architecture’s system architecture consists of a set of registers, data structures, and instructions designed to support basic system-level operations such as memory management, interrupt and exception handling, task management, and control of multiple processors (multiprocessing). Figure 2-1 provides a generalized summary of the system registers and data structures. 2-1 SYSTEM ARCHITECTURE OVERVIEW EFLAGS Register Physical Address Linear Address Code, Data or Stack Segment Task-State Segment (TSS) Task Code Data Stack Control Registers CR4 Segment Selector CR3 CR2 Register CR1 CR0 Global Descriptor MXCSR1 Table (GDT) Task Register Segment Sel. Interrupt Vector TSS Seg. Sel. Seg. Desc. TSS Desc. Seg. Desc. TSS Desc. LTD Desc. GDTR Trap Gate Local Descriptor Table (LDT) IDTR Call-Gate Segment Selector Seg. Desc. Call Gate LDTR Interrupt Handler Code Current Stack TSS Task-State Segment (TSS) Interrupt Descriptor Table (IDT) Interrupt Gate Task Gate Task Code Data Stack Exception Handler Code Current Stack TSS Protected Procedure Code Current Stack TSS Linear Address Space Dir Linear Addr. Linear Address Table Offset Page Directory Page Table Page Physical Addr. Pg. Dir. Entry Pg. Tbl. Entry 0 CR3* This page mapping example is for...
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