It consists of a set of model specific registers msrs

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Unformatted text preview: able 12-4. I/O Instruction Restart Field Values Value of Flag After Entry to SMM 00H 00H Value of Flag When Exiting SMM 00H FFH Action of Processor When Exiting SMM Does not re-execute trapped I/O instruction. Re-executes trapped I/O instruction. Note that the I/O instruction restart mechanism does not indicate the cause of the SMI. It is the responsibility of the SMI handler to examine the state of the processor to determine the cause of the SMI and to determine if an I/O instruction was interrupted and should be restarted upon exiting SMM. If an SMI interrupt is signaled on a non-I/O instruction boundary, setting the I/O instruction restart field to FFH prior to executing the RSM instruction will likely result in a program error. 12.12.1. Back-to-Back SMI Interrupts When I/O Instruction Restart Is Being Used If an SMI interrupt is signaled while the processor is servicing an SMI interrupt that occurred on an I/O instruction boundary, the processor will service the new SMI request before restarting the originally interrupted I/O instruction. If the I/O instruction restart field is set to FFH prior to returning from the second SMI handler, the EIP will point to an address different from the originally interrupted I/O instruction, which will likely lead to a program error. To avoid this situation, the SMI handler must be able to recognize the occurrence of back-to-back SMI interrupts 12-16 SYSTEM MANAGEMENT MODE (SMM) when I/O instruction restart is being used and insure that the handler sets the I/O instruction restart field to 00H prior to returning from the second invocation of the SMI handler. 12.13. SMM MULTIPLE-PROCESSOR CONSIDERATIONS The following should be noted when designing multiple-processor systems: • • • Any processor in a multiprocessor system can respond to an SMM. Each processor needs its own SMRAM space. This space can be in system memory or in a separate RAM. The SMRAMs for different processors can be overlapped in the same memory space. The only stipulation is that each processor needs its own state save area and its own dynamic data storage area. (Also, for the Pentium® and Intel486™ processors, the SMBASE address must be located on a 32-KByte boundary.) Code and static data can be shared among processors. Overlapping SMRAM spaces can be done more efficiently with the P6 family processors because they do not require that the SMBASE address be on a 32-KByte boundary. The SMI handler will need to initialize the SMBASE for each processor. Processors can respond to local SMIs through their SMI# pins or to SMIs received through the APIC interface. The APIC interface can distribute SMIs to different processors. Two or more processors can be executing in SMM at the same time. When operating Pentium® processors in dual processing (DP) mode, the SMIACT# pin is driven only by the MRM processor and should be sampled with ADS#. For additional details, refer to Chapter 14 of the Pentium® Processor Family User’s Manual, Volume 1. • • • • SMM is not re-entrant, because the SMRAM State Save Map is fixed relative to the SMBASE. If there is a need to support two or more processors in SMM mode at the same time then each processor should have dedicated SMRAM spaces. This can be done by using the SMBASE Relocation feature (refer to Section 12.11., “SMBASE Relocation”). 12-17 SYSTEM MANAGEMENT MODE (SMM) 12-18 13 Machine-Check Architecture MACHINE-CHECK ARCHITECTURE CHAPTER 13 MACHINE-CHECK ARCHITECTURE This chapter describes the P6 family’s machine-check architecture and machine-check exception mechanism. Refer to Chapter 5, Interrupt and Exception Handling for more information on the machine-check exception. A brief description of the Pentium® processor’s machine check capability is also given. 13.1. MACHINE-CHECK EXCEPTIONS AND ARCHITECTURE The P6 family of processors implement a machine-check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as system bus errors, ECC errors, parity errors, cache errors, and TLB errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs for recording the errors that are detected. The processor signals the detection of a machine-check error by generating a machine-check exception (#MC). A machine-check exception is generally an abort class exception. The implementation of the machine-check architecture, does not ordinarily permit the processor to be restarted reliably after generating a machine-check exception; however, the machine-check-exception handler can collect information about the machinecheck error from the machine-check MSRs. 13.2. COMPATIBILITY WITH PENTIUM® PROCESSOR The P6 family processors support and extend the machine-check exception mechanism used in the Pentium® processor. The Pentium® processor reports the following machine-check errors: • • Data parity errors during read cycles. Unsuccessful completion of a bus cycle. These errors are reported through the P5_MC_TYPE and P5_MC_ADDR MSRs, which...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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