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Unformatted text preview: CR0 was set. The processor executed a floating-point, MMX™ or SIMD floating-point (excluding prefetch, sfence or streaming store instructions) instruction while the TS flag of register CR0 was set. The processor executed a WAIT or FWAIT instruction while the MP and TS flags of register CR0 were set. The EM flag is set when the processor does not have an internal floating-point unit. An exception is then generated each time a floating-point instruction is encountered, allowing an exception handler to call floating-point instruction emulation routines. The TS flag indicates that a context switch (task switch) has occurred since the last time a floating-point, MMX™ or SIMD floating-point (excluding prefetch, sfence or streaming store instructions) instruction was executed, but that the context of the FPU was not saved. When the TS flag is set, the processor generates a device-not-available exception each time a floatingpoint, MMX™ or SIMD floating-point (excluding prefetch, sfence or streaming store instructions) instruction is encountered. The exception handler can then save the context of the FPU before it executes the instruction. Refer to Section 2.5., “Control Registers”, in Chapter 2, System Architecture Overview, for more information about the TS flag. The MP flag in control register CR0 is used along with the TS flag to determine if WAIT or FWAIT instructions should generate a device-not-available exception. It extends the function of the TS flag to the WAIT and FWAIT instructions, giving the exception handler an opportunity to save the context of the FPU before the WAIT or FWAIT instruction is executed. The MP flag is provided primarily for use with the Intel286 and Intel386™ DX processors. For programs running on the P6 family, Pentium®, or Intel486™ DX processors, or the Intel 487 SX coprocessors, the MP flag should always be set; for programs running on the Intel486™ SX processor, the MP flag should be clear. Exception Error Code None. Saved Instruction Pointer The saved contents of CS and EIP registers point to the floating-point instruction or the WAIT/FWAIT instruction that generated the exception. 5-30 INTERRUPT AND EXCEPTION HANDLING Program State Change A program-state change does not accompany a device-not-available fault, because the instruction that generated the exception is not executed. If the EM flag is set, the exception handler can then read the floating-point instruction pointed to by the EIP and call the appropriate emulation routine. If the MP and TS flags are set or the TS flag alone is set, the exception handler can save the context of the FPU, clear the TS flag, and continue execution at the interrupted floating-point or WAIT/FWAIT instruction. 5-31 INTERRUPT AND EXCEPTION HANDLING Interrupt 8—Double Fault Exception (#DF)
Exception Class Description Indicates that the processor detected a second exception while calling an exception handler for a prior exception. Normally, when the processor detects another exception while trying to call an exception handler, the two exceptions can be handled serially. If, however, the processor cannot handle them serially, it signals the double-fault exception. To determine when two faults need to be signaled as a double fault, the processor divides the exceptions into three classes: benign exceptions, contributory exceptions, and page faults (refer to Table 5-4).
Table 5-4. Interrupt and Exception Classes
Class Benign Exceptions and Interrupts Vector Number 1 2 3 4 5 6 7 9 16 17 18 19 All All 0 10 11 12 13 14 Description Debug Exception NMI Interrupt Breakpoint Overflow BOUND Range Exceeded Invalid Opcode Device Not Available Coprocessor Segment Overrun Floating-Point Error Alignment Check Machine Check SIMD floating-point extensions INT n INTR Divide Error Invalid TSS Segment Not Present Stack Fault General Protection Page Fault Abort. Contributory Exceptions Page Faults Table 5-5 shows the various combinations of exception classes that cause a double fault to be generated. A double-fault exception falls in the abort class of exceptions. The program or task cannot be restarted or resumed. The double-fault handler can be used to collect diagnostic information about the state of the machine and/or, when possible, to shut the application and/or system down gracefully or restart the system. A segment or page fault may be encountered while prefetching instructions; however, this behavior is outside the domain of Table 5-5. Any further faults generated while the processor is attempting to transfer control to the appropriate fault handler could still lead to a double-fault sequence. 5-32 INTERRUPT AND EXCEPTION HANDLING Table 5-5. Conditions for Generating a Double Fault
Second Exception First Exception Benign Contributory Page Fault Benign Handle Exceptions Serially Handle Exceptions Serially Handle Exceptions Serially Contributory Handle Exceptions Serially Generate a Double Fault Generate a Double Fault Page Fault Handle Exceptions Serially Handle Exce...
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