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Likewise the interconnect error conditions are

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Unformatted text preview: orted and not the register bank reporting it. There are two types of MCA error codes: simple error codes and compound error codes. 13-8 MACHINE-CHECK ARCHITECTURE 13.6.1. Simple Error Codes Table 13-1 shows the simple error codes. These unique codes indicate global error information. Table 13-1. Simple Error Codes Error Code No Error Unclassified Microcode ROM Parity Error External Error FRC Error Internal Unclassified Binary Encoding 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0011 0000 0000 0000 0100 0000 01xx xxxx xxxx Meaning No error has been reported to this bank of error-reporting registers. This error has not been classified into the MCA error classes. Parity error in internal microcode ROM The BINIT# from another processor caused this processor to enter machine check. FRC (functional redundancy check) master/slave error Internal unclassified errors 13.6.2. Compound Error Codes The compound error codes describe errors related to the TLBs, memory, caches, bus and interconnect logic. A set of sub-fields is common to all of the compound error encodings. These subfields describe the type of access, level in the memory hierarchy, and type of request. Table 13-2 shows the general form of the compound error codes. The interpretation column indicates the name of a compound error. The name is constructed by substituting mnemonics from Tables 13-2 through 13-6 for the sub-field names given within curly braces. For example, the error code ICACHEL1_RD_ERR is constructed from the form: {TT}CACHE{LL}_{RRRR}_ERR where {TT} is replaced by I, {LL} is replaced by L1, and {RRRR} is replaced by RD. The 2-bit TT sub-field (refer to Table 13-2) indicates the type of transaction (data, instruction, or generic). It applies to the TLB, cache, and interconnect error conditions. The generic type is reported when the processor cannot determine the transaction type. Table 13-2. General Forms of Compound Error Codes Type TLB Errors Memory Hierarchy Errors Bus and Interconnect Errors Form 0000 0000 0001 TTLL 0000 0001 RRRR TTLL 0000 1PPT RRRR IILL Interpretation {TT}TLB{LL}_ERR {TT}CACHE{LL}_{RRRR}_ERR BUS{LL}_{PP}_{RRRR}_{II}_{T}_ERR 13-9 MACHINE-CHECK ARCHITECTURE Table 13-3. Encoding for TT (Transaction Type) Sub-Field Transaction Type Instruction Data Generic Mnemonic I D G Binary Encoding 00 01 10 The 2-bit LL sub-field (refer to Table 13-4) indicates the level in the memory hierarchy where the error occurred (level 0, level 1, level 2, or generic). The LL sub-field also applies to the TLB, cache, and interconnect error conditions. The P6 family processors support two levels in the cache hierarchy and one level in the TLBs. Again, the generic type is reported when the processor cannot determine the hierarchy level. Table 13-4. Level Encoding for LL (Memory Hierarchy Level) Sub-Field Hierarchy Level Level 0 Level 1 Level 2 Generic Mnemonic L0 L1 L2 LG Binary Encoding 00 01 10 11 The 4-bit RRRR sub-field (refer to Table 13-5) indicates the type of action associated with the error. Actions include read and write operations, prefetches, cache evictions, and snoops. Generic error is returned when the type of error cannot be determined. Generic read and generic write are returned when the processor cannot determine the type of instruction or data request that caused the error. Eviction and Snoop requests apply only to the caches. All of the other requests apply to TLBs, caches and interconnects. Table 13-5. Encoding of Request (RRRR) Sub-Field Request Type Generic Error Generic Read Generic Write Data Read Data Write Instruction Fetch Prefetch Eviction Snoop Mnemonic ERR RD WR DRD DWR IRD PREFETCH EVICT SNOOP Binary Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 13-10 MACHINE-CHECK ARCHITECTURE The bus and interconnect errors are defined with the 2-bit PP (participation), 1-bit T (time-out), and 2-bit II (memory or I/O) sub-fields, in addition to the LL and RRRR sub-fields (refer to Table 13-6). The bus error conditions are implementation dependent and related to the type of bus implemented by the processor. Likewise, the interconnect error conditions are predicated on a specific implementation-dependent interconnect model that describes the connections between the different levels of the storage hierarchy. The type of bus is implementation dependent, and as such is not specified in this document. A bus or interconnect transaction consists of a request involving an address and a response. Table 13-6. Encodings of PP, T, and II Sub-Fields Sub-Field PP (Participation) Transaction Local processor originated request Local processor responded to request Local processor observed error as third party Generic T (Time-out) Request timed out Request did not time out II (Memory or I/O) Memory Access Reserved I/O Other transaction IO TIMEOUT NOTIMEOUT M Mnemonic SRC RES OBS Binary Encoding 00 01 10 11 1 0 00 01 10 11 13.6.3. Interpreting the Machine-Check Error Codes for External Bus Errors Table 13-7 gives additional information for interpreting the MCA error...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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