Likewise when a floating point value written into a

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Unformatted text preview: hen remapping a page that was previously mapped as a cacheable memory type to a WC page, an operating system can avoid this type of aliasing by: • • • • Removing the previous mapping to a cacheable memory type in the page tables; that is, make them not present. Flushing the TLBs of processors that may have used the mapping, even speculatively. Creating a new mapping to the same physical address with a new memory type, for instance, WC. Flushing the caches on all processors that may have used the mapping previously. Operating systems that use a Page Directory as a Page Table and enable Page Size Extensions must carefully scrutinize the use of the PATi index bit for the 4 KB Page-Table Entries. The PATi index bit for a PTE (bit 7) corresponds to the page size bit in a PDE. Therefore, the operating system can only utilize PAT entries PA0-3 when setting the caching type for a page table that is also used as a page directory. If the operating system attempts to use PAT entries PA4-7 when using this memory as a page table, it effectively sets the PS bit for the access to this memory as a page directory. 9-39 MEMORY CACHE CONTROL 9-40 10 MMX™ Technology System Programming MMX™ TECHNOLOGY SYSTEM PROGRAMMING CHAPTER 10 MMX™ TECHNOLOGY SYSTEM PROGRAMMING This chapter describes those features of the MMX™ technology that must be considered when designing or enhancing an operating system to support MMX™ technology. It covers MMX™ instruction set emulation, the MMX™ state, aliasing of MMX™ registers, saving MMX™ state, task and context switching considerations, exception handling, and debugging. 10.1. EMULATION OF THE MMX™ INSTRUCTION SET The Intel Architecture does not support emulation of the MMX™ technology, as it does for floating-point instructions. The EM flag in control register CR0 (provided to invoke emulation of floating-point instructions) cannot be used for MMX™ technology emulation. If an MMX™ instruction is executed when the EM flag is set, an invalid opcode (UD#) exception is generated. 10.2. THE MMX™ STATE AND MMX™ REGISTER ALIASING The MMX™ state consists of eight 64-bit registers (MM0 through MM7). These registers are aliased to the 64-bit mantissas (bits 0 through 63) of floating-point registers R0 through R7 (see Figure 10-2). Note that the MMX™ registers are mapped to the physical locations of the floating-point registers (R0 through R7), not to the relative locations of the registers in the floating-point register stack (ST0 through ST7). As a result, the MMX™ register mapping is fixed and is not affected by value in the Top Of Stack (TOS) field in the floating-point status word (bits 11 through 13). When a value is written into an MMX™ register using an MMX™ instruction, the value also appears in the corresponding floating-point register in bits 0 through 63. Likewise, when a floating-point value written into a floating-point register by a floating-point instruction, the mantissa of that value also appears in a the corresponding MMX™ register. The execution of MMX™ instructions have several side effects on the FPU state contained in the floating-point registers, the FPU tag word, and the FPU the status word. These side effects are as follows: • • • When an MMX™ instruction writes a value into an MMX register, at the same time, bits 64 through 79 of the corresponding floating-point register (the exponent field and the sign bit) are set to all 1s. When an MMX™ instruction (other than the EMMS instruction) is executed, each of the tag fields in the FPU tag word is set to 00B (valid). (See also Section 10.2.1., “Effect of MMX™ and Floating-Point Instructions on the FPU Tag Word”.) When the EMMS instruction is executed, each tag field in the FPU tag word is set to 11B (empty). 10-1 MMX™ TECHNOLOGY SYSTEM PROGRAMMING • Each time an MMX™ instruction is executed, the TOS value is set to 000B. FPU Tag Register 00 00 00 00 00 00 00 00 79 64 63 Floating-Point Registers Mantissa 0 R7 R6 R5 R4 R3 R2 R1 R0 FPU Status Register 13 11 000 TOS 63 MMXTM Registers 0 MM7 MM6 MM5 MM4 MM3 MM2 MM1 TOS = 0 MM0 Figure 10-1. Mapping of MMX™ Registers to Floating-Point Registers Execution of MMX™ instructions does not affect the other bits in the FPU status word (bits 0 through 10 and bits 14 and 15) or the contents of the other FPU registers that comprise the FPU state (the FPU control word, instruction pointer, data pointer, or opcode registers). Table 10-1 summarizes the effects of the MMX™ instructions on the FPU state. 10-2 MMX™ TECHNOLOGY SYSTEM PROGRAMMING Table 10-1. Effects of MMX™ Instructions on FPU State MMX™ Instruction Type Read from MMn register Write to MMn register EMMS NOTE: MMn refers to one MMX™ register; Rn refers to corresponding floating-point register. TOS Field of FPU Status Word 000B 000B 000B Other FPU Registers Unchanged Unchanged Unchanged Exponent Bits and Sign Bit of Rn Unchanged Set to all 1s Unchanged FPU Tag Word All tags set to 00B (Valid) All tags set to 00B (Valid) All fields set to 11B (Empty) Mantissa of Rn Unchanged Overwritten with MMX™ data Unchanged 10.2.1. Effect of MMX™ and Floating-Point Instructions on the FPU Tag...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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