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Mcstatusaddrv mcstatusdam mcstatusmcacod

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Unformatted text preview: nds to be issued via cache configuration accesses mechanism. Also receives L2 lookup response Reserved Processor number2 Disable = 1 Enable = 0 Reserved User supplied ECC Reserved L2 Hit Reserved State from L2 Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00 Way from L2 Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11 Way to L2 Reserved State to L2 L2 Command Data Read w/ LRU update (RLU) Tag Read w/ Data Read (TRR) Tag Inquire (TI) L2 Control Register Read (CR) L2 Control Register Write (CW) Tag Write w/ Data Read (TWR) Tag Write w/ Data Write (TWW) Tag Write (TW) Trigger register: used to initiate a cache configuration accesses access, Write only with Data=0. Busy register: indicates when a cache configuration accesses L2 command is in progress. D[0] = 1 = BUSY Bit Description BIOS Update Signature Register or Chunk 3 data register D[63:0]: used to write to and read from the L2 depending on the usage model C1H C2H FEH 116 193 194 254 278 BL_CR_CTL[63:22] BBL_CR_CTL[21] BBL_CR_CTL[20:19] BBL_CR_CTL[18] BBL_CR_CTL[17] BBL_CR_CTL[16] BBL_CR_CTL[15:14] BBL_CR_CTL[13:12] BBL_CR_CTL[11:10] BBL_CR_CTL[9:8] BBL_CR_CTL[7] BBL_CR_CTL[6:5] BBL_CR_CTL[4:0] 01100 01110 01111 00010 00011 010 + MESI encode 111 + MESI encode 100 + MESI encode 11A 11B 282 283 BBL_CR_TRIG BBL_CR_BUSY B-4 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.) Register Address Hex 11E Dec 286 Register Name BBL_CR_CTL3 BBL_CR_CTL3[63:26] BBL_CR_CTL3[25] BBL_CR_CTL3[24] BBL_CR_CTL3[23] BBL_CR_CTL3[22:20] 111 110 101 100 011 010 001 000 BBL_CR_CTL3[19] BBL_CR_CTL3[18] BBL_CR_CTL3[17:13 00001 00010 00100 01000 10000 BBL_CR_CTL3[12:11] BBL_CR_CTL3[10:9] 00 01 10 11 BBL_CR_CTL3[8] BBL_CR_CTL3[7] BBL_CR_CTL3[6] BBL_CR_CTL3[5] BBL_CR_CTL3[4:1] BBL_CR_CTL3[0] 179H 17AH 17BH 186H 377 378 379 390 MCG_CAP MCG_STATUS MCG_CTL EVNTSEL0 7:0 Event Select (Refer to Performance Counter section for a list of event encodings) UMASK: Unit Mask Register Set to 0 to enable all count options USER: Controls the counting of events at Privilege levels of 1, 2, and 3 Bit Description Control register 3: used to configure the L2 Cache Reserved Cache bus fraction (read only) Reserved L2 Hardware Disable (read only) L2 Physical Address Range support 64Gbytes 32Gbytes 16Gbytes 8Gbytes 4Gbytes 2Gbytes 1Gbytes 512Mbytes Reserved Cache State error checking enable (read/write) Cache size per bank (read/write) 256Kbytes 512Kbytes 1Mbyte 2Mbyte 4Mbytes Number of L2 banks (read only) L2 Associativity (read only) Direct Mapped 2 Way 4 Way Reserved L2 Enabled (read/write) CRTN Parity Check Enable (read/write) Address Parity Check Enable (read/write) ECC Check Enable (read/write) L2 Cache Latency (read/write) L2 Configured (read/write) 15:8 16 B-5 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.) Register Address Hex Dec 17 18 Register Name Bit Description OS: Controls the counting of events at Privilege level of 0 E: Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration PC: Enabled the signaling of performance counter overflow via BP0 pin INT: Enables the signaling of counter overflow via input to APIC 1 = Enable 0 = Disable ENABLE: Enables the counting of performance events in both counters 1 = Enable 0 = Disable INV: Inverts the result of the CMASK condition 1 = Inverted 0 = Non-Inverted CMASK: Counter Mask 19 20 22 23 31:24 187H 391 EVNTSEL1 7:0 Event Select (Refer to Performance Counter section for a list of event encodings) UMASK: Unit Mask Register Set to Zero to enable all count options USER: Controls the counting of events at Privilege levels of 1, 2, and 3 OS: Controls the counting of events at Privilege level of 0 E: Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration PC: Enabled the signaling of performance counter overflow via BP0 pin. 15:8 16 17 18 19 B-6 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.) Register Address Hex Dec 20 Register Name Bit Description INT: Enables the signaling of counter overflow via input to APIC 1 = Enable 0 = Disable INV: Inverts the result of the CMASK condition 1 = Inverted 0 = Non-Inverted CMASK: Counter Mask 23 31:24 1D9H 473 DEBUGCTLMSR 0 1 2 3 4 5 6 13:7 14 15 1DBH 1DCH 1DDH 1DEH 1E0H 475 476 477 478 480 LASTBRANCHFROMIP LASTBRANCHTOIP LASTINTFROMIP LASTINTTOIP ROB_CR_BKUPTMPDR6 1:0 2 200H 201H 202H 203H 204H 205H 512 513 514 515 516 517 MTRRphysBase0 MTRRphysMask0 MTRRphysBase1 MTRRphysMask1 MTRRphysBase2 MTRRphysMask2 Enable/Disable Last Branch Records Branch Trap Flag Performance Monitoring/Break Point Pins Performance Monitoring/Break Point Pins Performance Monitoring/Break Point Pins Performance Monitoring/Break Point Pins Enable/Disable Execution Trace Messages Reserved Enable/Disable Execution Trace Messages Enable/Disable Execution Trace Messages Reserved Fast String Enable bit. Default is enabled B-7 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.) Register Address Hex 206H 207H 208H 209H 20AH 20BH 20CH 20DH 20EH 20FH 250H 258H 259H 268H 269H 26AH 26BH 26CH 26DH 26EH 26FH 2FFH Dec 518 519 520 521 522...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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