IntelSoftwareDevelopersManual

Mov mov and or icrlow write address of icr low dword

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: er (default is 0): MOV MOV AND MOV ESI, APIC_ID; address of local APIC ID register EAX, [ESI] EAX, 0F000000H; zero out all other bits except APIC ID BOOT_ID, EAX; save in memory Save the ID in the configuration RAM (optional). 7. Determine APIC ID of the secondary processor and save it in the configuration RAM (optional). MOV EAX, BOOT_ID XOR EAX, 100000H; toggle lower bit of ID field (bit 24) MOV SECOND_ID, EAX 8. Convert the base address of the 4-KByte page for the secondary processor’s bootup code into 8-bit vector. The 8-bit vector defines the address of a 4-KByte page in the real-address mode address space (1-MByte space). For example, a vector of 0BDH specifies a start-up memory address of 000BD000H. Use steps 9 and 10 to use the LVT APIC error handling entry to deal with unsuccessful delivery of the start-up IPI. 9. Enable the local APIC by writing to spurious vector register (SVR). This is required to do APIC error handling via the local vector table. MOV MOV OR MOV ESI, SVR ; address of SVR EAX, [ESI] EAX, APIC_ENABLED; set bit 8 to enable (0 on reset) [ESI], EAX C-2 DUAL-PROCESSOR (DP) BOOTUP SEQUENCE EXAMPLE (SPECIFIC 10. Program LVT3 (APIC error interrupt vector) of the local vector table with an 8-bit vector for handling APIC errors. MOV ESI, LVT3 MOV EAX, [ESI] AND EAX, FFFFFF00H; clear out previous vector OR EAX, 000000xxH; xx is the 8-bit vector for APIC error ; handling. MOV [ESI], EAX 11. Write APIC ICRH with address of the secondary processor’s APIC. MOV MOV AND OR ICR_HI ; address of ICR high dword [ESI] ; get high word of ICR 0F0FFFFFFH; zero out ID Bits SECOND_ID; write ID into appropriate bits - don’t ; affect reserved bits MOV [ESI], SECOND_ID; write upgrade ID to destination field ESI, EAX, EAX, EAX, 12. Set the timer with an appropriate value (~100 milliseconds). 13. Write APIC ICRL to send a start-up IPI message to the secondary processor via the APIC. MOV MOV AND OR ICR_LOW; write address of ICR low dword [ESI] ; get low dword of ICR 0FFF0F800H; zero out delivery mode and vector fields 000006xxH; 6 selects delivery mode 110 (StartUp IPI) ; xx should be vector of 4kb page as ; computed in Step 8. MOV [ESI], EAX ESI, EAX, EAX, EAX, 14. Configure the APIC as appropriate. C-3 C.2. SECONDARY PROCESSOR’S SEQUENCE OF EVENTS FOLLOWING RECEIPT OF START-UP IPI If the secondary processor’s APIC is to be used for symmetric multiprocessing, the secondary processor must undertake the following steps: 1. Switch to protected mode to access the APIC addresses. 2. Initialize its local APIC by writing to bit 8 of the SVR register and programming its LVT3 for error handling. 3. Configure the APIC as appropriate. 4. Enable interrupts. 5. (Optional.) Execute the CPUID instruction and write the results into the configuration RAM. 6. Do either of the following: — Execute a HALT instruction and wait for an IPI from the operating system. — Continue execution. D Multiple-Processor (MP) Bootup Sequence Example (Specific to P6 Family Processors) APPENDIX D MULTIPLE-PROCESSOR (MP) BOOTUP SEQUENCE EXAMPLE (SPECIFIC TO P6 FAMILY PROCESSORS) The following example illustrates the use of the MP protocol to boot two P6 family processors in a multiple-processor (MP) system and initialize their APICs. The primary processor (the processor that won the “race for the flag”) is called the boot strap processor (BSP) and the secondary processor is called the application processor (AP). The following constants and data definitions are used in the accompanying code examples. They are based on the addresses of the APIC registers as defined in Table 7-1 in Chapter 7. ICR_LOW ICR_HI SVR APIC_ID LVT3 APIC_ENABLED BOOT_ID SECOND_ID EQU 0FEE00300H EQU 0FEE00310H EQU 0FEE000F0H EQU 0FEE00020H EQU 0FEE00370H EQU 100H DW ? DW ? D.1. BSP’S SEQUENCE OF EVENTS 1. The BSP boots at the Intel Architecture address and executes until it is ready to activate the AP. 2. Initialization software should execute the CPUID instruction to determine if the BSP is a “GenuineIntel.” The values of EAX and EDX should be saved into a configuration RAM space for use later. 3. The following operation can be used to detect the AP: Set a timer before sending the start-up IPI to the AP. In the AP’s initialization routine, it should write a value into memory indicating its presence. The BSP can then use the timer expiration to check if something has been written into memory. If the timer expires and nothing has been written into memory, the AP is not present or some error has occurred. 4. Load start-up code for the AP to execute into a 4-KByte page in the lower 1 MByte of memory. D-1 MULTIPLE-PROCESSOR (MP) BOOTUP SEQUENCE EXAMPLE 5. Switch to protected mode (to access APIC address space above 1 MByte) or change the APIC base to less than 1 MByte and insure it is mapped to an uncached (UC) memory type. 6. Determine the BSP’s APIC ID from the local APIC ID register (default is 0): MOV MOV AND MOV ESI, APIC_ID; address of local APIC ID...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online