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Unformatted text preview: ng the execution of an MMX™ instruction: • Exceptions during memory accesses: — Stack-segment fault (#SS). — General protection (#GP). — Page fault (#PF). — Alignment check (#AC), if alignment checking is enabled. • System exceptions: — Invalid Opcode (#UD), if the EM flag in control register CR0 is set when an MMX™ instruction is executed. (Refer to Section 10.1., “Emulation of the MMX™ Instruction Set”). 10-7 MMX™ TECHNOLOGY SYSTEM PROGRAMMING — Device not available (#NM), if an MMX™ instruction is executed when the TS flag in control register CR0 is set. (See Refer to Section 10.4.1., “Using the TS Flag in Control Register CR0 to Control MMX™/FPU State Saving”.) • • Floating-point error (#MF). (See Refer to Section 10.5.1., “Effect of MMX™ Instructions on Pending Floating-Point Exceptions”.) Other exceptions can occur indirectly due to the faulty execution of the exception handlers for the above exceptions. For example, if a stack-segment fault (#SS) occurs due to MMX™ instructions, the interrupt gate for the stack-segment fault can direct the processor to invalid TSS, causing an invalid TSS exception (#TS) to be generated. 10.5.1. Effect of MMX™ Instructions on Pending Floating-Point Exceptions
If a floating-point exception is pending and the processor encounters an MMX™ instruction, the processor generates a floating-point error (#MF) prior to executing the MMX™ instruction, to allow the exception to be handled by the floating-point error exception handler. While the handler is executing, the FPU state is maintained and is visible to the handler. Upon returning from the exception handler, the MMX™ instruction is executed, which will alter the FPU state, as described in Section 10.2., “The MMX™ State and MMX™ Register Aliasing”. 10.6. DEBUGGING
The debug facilities of the Intel Architecture operate in the same manner when executing MMX™ instructions as when executing other Intel Architecture instructions. These facilities enable debuggers to debug MMX™ technology code. To correctly interpret the contents of the MMX™ or FPU registers from the FXSAVE/FSAVE image in memory, a debugger needs to take account of the relationship between the floatingpoint register’s logical locations relative to TOS and the MMX™ register’s physical locations. In the floating-point context, STn refers to a floating-point register at location n relative to the TOS. However, the tags in the FPU tag word are associated with the physical locations of the floating-point registers (R0 through R7). The MMX™ registers always refer to the physical locations of the registers (with MM0 through MM7 being mapped to R0 through R7). In Figure 10-2, the inner circle refers to the physical location of the floating-point and MMX™ registers. The outer circle refers to the floating-point registers’s relative location to the current TOS. 10-8 MMX™ TECHNOLOGY SYSTEM PROGRAMMING FP “push” ST0 FP “pop” ST1 MM1 MM7 ST2 MM6 MM5 ST6 FP “push ST7 MM7 MM6 MM5 MM0 (R0) MM2 (R2) MM3 MM4 MM0 (R0) MM1 TOS MM2 (R2) MM3 MM4 ST7 TOS ST0 FP “pop” ST1 Case A: TOS=0 Case B: TOS=2 Outer circle = FP register’s logical location relative to TOS Inner circle = FPU tags = MMX™ register’s location = FP registers’s physical location Figure 10-3. Mapping of MMX™ Registers to Floating-Point (FP) Registers When the TOS equals 0 (case A in Figure 10-2), ST0 points to the physical location R0 on the floating-point stack. MM0 maps to ST0, MM1 maps to ST1, and so on. When the TOS equals 2 (case B in Figure 10-2), ST0 points to the physical location R2. MM0 maps to ST6, MM1 maps to ST7, MM2 maps to ST0, and so on. 10-9 MMX™ TECHNOLOGY SYSTEM PROGRAMMING 10-10 11
Streaming SIMD Extensions System Programming CHAPTER 11 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING
This chapter describes those features of the Streaming SIMD Extensions that must be considered when designing or enhancing an operating system to support the Pentium® III processor. It covers extensions emulation, the new SIMD floating-point architectural state, similarities to MMX™ technology, task and context switching considerations, exception handling, and debugging. 11.1. EMULATION OF THE STREAMING SIMD EXTENSIONS
The Intel Architecture does not support emulation of the Streaming SIMD Extensions, as it does for floating-point instructions. The EM flag in control register CR0 (provided to invoke emulation of floating-point instructions) cannot be used for Streaming SIMD Extensions emulation. If a Streaming SIMD Extensions instruction is executed when the EM flag is set (CR0.EM), an invalid opcode (UD#/INT6) exception is generated instead of a device not available exception (NM#/INT7). 11.2. MMX™ STATE AND STREAMING SIMD EXTENSIONS
The SIMD-integer instructions of the Streaming SIMD Extensions use the same registers as the MMX™ technology instructions. In addition they have been implemented so the same rules for MMX...
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