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Unformatted text preview: MEMORY MANAGEMENT Linear Address 31 22 21 12 11 Table Directory 0 Offset 12 4-KByte Page Physical Address 10 Page Directory 10 Page Table Page-Table Entry Directory Entry 32* CR3 (PDBR) *32 bits aligned onto a 4-KByte boundary. 1024 PDE ∗ 1024 PTE = 220 Pages Figure 3-12. Linear Address Translation (4-KByte Pages) To select the various table entries, the linear address is divided into three sections: • • • Page-directory entry—Bits 22 through 31 provide an offset to an entry in the page directory. The selected entry provides the base physical address of a page table. Page-table entry—Bits 12 through 21 of the linear address provide an offset to an entry in the selected page table. This entry provides the base physical address of a page in physical memory. Page offset—Bits 0 through 11 provides an offset to a physical address in the page. Memory management software has the option of using one page directory for all programs and tasks, one page directory for each task, or some combination of the two. 22.214.171.124. LINEAR ADDRESS TRANSLATION (4-MBYTE PAGES) Figure 3-12 shows how a page directory can be used to map linear addresses to 4-MByte pages. The entries in the page directory point to 4-MByte pages in physical memory. This paging method can be used to map up to 1024 pages into a 4-GByte linear address space. 3-21 PROTECTED-MODE MEMORY MANAGEMENT 31 Linear Address 22 21 Offset Directory 22 0 4-MByte Page Physical Address 10 Page Directory Directory Entry 32* 1024 PDE = 1024 Pages CR3 (PDBR) *32 bits aligned onto a 4-KByte boundary. Figure 3-13. Linear Address Translation (4-MByte Pages) The 4-MByte page size is selected by setting the PSE flag in control register CR4 and setting the page size (PS) flag in a page-directory entry (refer to Figure 3-14). With these flags set, the linear address is divided into two sections: • • Page directory entry—Bits 22 through 31 provide an offset to an entry in the page directory. The selected entry provides the base physical address of a 4-MByte page. Page offset—Bits 0 through 21 provides an offset to a physical address in the page.
NOTE (For the Pentium processor only.) When enabling or disabling large page sizes, the TLBs must be invalidated (flushed) after the PSE flag in control register CR4 has been set or cleared. Otherwise, incorrect page translation might occur due to the processor using outdated page translation information stored in the TLBs. Refer to Section 9.10., “Invalidating the Translation Lookaside Buffers (TLBs)”, in Chapter 9, Memory Cache Control, for information on how to invalidate the TLBs. 126.96.36.199. MIXING 4-KBYTE AND 4-MBYTE PAGES ® When the PSE flag in CR4 is set, both 4-MByte pages and page tables for 4-KByte pages can be accessed from the same page directory. If the PSE flag is clear, only page tables for 4-KByte pages can be accessed (regardless of the setting of the PS flag in a page-directory entry). A typical example of mixing 4-KByte and 4-MByte pages is to place the operating system or executive’s kernel in a large page to reduce TLB misses and thus improve overall system performance. The processor maintains 4-MByte page entries and 4-KByte page entries in separate 3-22 PROTECTED-MODE MEMORY MANAGEMENT TLBs. So, placing often used code such as the kernel in a large page, frees up 4-KByte-page TLB entries for application programs and tasks. 3.6.3. Base Address of the Page Directory The physical address of the current page directory is stored in the CR3 register (also called the page directory base register or PDBR). (Refer to Figure 2-5 and Section 2.5., “Control Registers” in Chapter 2, System Architecture Overview for more information on the PDBR.) If paging is to be used, the PDBR must be loaded as part of the processor initialization process (prior to enabling paging). The PDBR can then be changed either explicitly by loading a new value in CR3 with a MOV instruction or implicitly as part of a task switch. (Refer to Section 6.2.1., “Task-State Segment (TSS)” in Chapter 6, Task Management for a description of how the contents of the CR3 register is set for a task.) There is no present flag in the PDBR for the page directory. The page directory may be notpresent (paged out of physical memory) while its associated task is suspended, but the operating system must ensure that the page directory indicated by the PDBR image in a task's TSS is present in physical memory before the task is dispatched. The page directory must also remain in memory as long as the task is active. 3.6.4. Page-Directory and Page-Table Entries Figure 3-14 shows the format for the page-directory and page-table entries when 4-KByte pages and 32-bit physical addresses are being used. Figure 3-14 shows the format for the page-directory entries when 4-MByte pages and 32-bit physical addresses are being used. Refer to Section 3.8., “Physical Address Extension” for the format of page-directory and page-table entries when the physical address...
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