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Unformatted text preview: l486™ processor does. When this flag is set, the virtual mode extension provides the following enhancements to virtual-8086 mode: • • Speeds up the handling of software-generated interrupts in virtual-8086 mode by allowing the processor to bypass the virtual-8086 monitor and redirect software interrupts back to the interrupt handlers that are part of the currently running 8086 program. Supports virtual interrupts for software written to run on the 8086 processor. The IOPL value interacts with the VME flag and the bits in the interrupt redirection bit map to determine how specific software interrupts should be handled. The software interrupt redirection bit map (refer to Figure 16-5) is a 32-byte field in the TSS. This map is located directly below the I/O permission bit map in the TSS. Each bit in the interrupt redirection bit map is mapped to an interrupt vector. Bit 0 in the interrupt redirection bit map (which maps to vector zero in the interrupt table) is located at the I/O base map address in the TSS minus 32 bytes. When a bit in this bit map is set, it indicates that the associated software interrupt (interrupt generated with an INT n instruction) should be handled through the protected-mode IDT and interrupt and exception handlers. When a bit in this bit map is clear, the processor redirects the associated software interrupt back to the interrupt table in the 8086 program (located at linear address 0 in the program’s address space). 16-23 8086 EMULATION NOTE The software interrupt redirection bit map does not affect hardware generated interrupts and exceptions. Hardware generated interrupts and exceptions are always handled by the protected-mode interrupt and exception handlers.
Table 16-2. Software Interrupt Handling Methods While in Virtual-8086 Mode
Bit in Redir. Bitmap* X Method 1 VME 0 IOPL 3 Processor Action Interrupt directed to a protected-mode interrupt handler: - Clears VM and TF flags - If serviced through interrupt gate, clears IF flag - Switches to privilege-level 0 stack - Pushes GS, FS, DS and ES onto privilege-level 0 stack - Clears GS, FS, DS and ES to 0 - Pushes SS, ESP, EFLAGS, CS and EIP of interrupted task onto privilege-level 0 stack - Sets CS and EIP from interrupt gate Interrupt directed to protected-mode general-protection exception (#GP) handler. Interrupt directed to a protected-mode general-protection exception (#GP) handler; VIF and VIP flag support for handling class 2 maskable hardware interrupts. Interrupt directed to protected-mode interrupt handler: (refer to method 1 processor action). Interrupt redirected to 8086 program interrupt handler: - Pushes EFLAGS with NT cleared and IOPL set to 0 - Pushes CS and EIP (lower 16 bits only) - Clears IF flag - Clears TF flag - Loads CS and EIP (lower 16 bits only) from selected entry in the interrupt vector table of the current virtual-8086 task Interrupt redirected to 8086 program interrupt handler; VIF and VIP flag support for handling class 2 maskable hardware interrupts: - Pushes EFLAGS with IOPL set to 3 and VIF copied to IF - Pushes CS and EIP (lower 16 bits only) - Clears the VIF flag - Clears TF flag - Loads CS and EIP (lower 16 bits only) from selected entry in the interrupt vector table of the current virtual-8086 task 2 3 0 1 <3 <3 X 1 4 5 1 1 3 3 1 0 6 1 <3 0 NOTE: * When set to 0, software interrupt is redirected back to the 8086 program interrupt handler; when set to 1, interrupt is directed to protected-mode handler. 16-24 8086 EMULATION Last byte of bit map must be followed by a byte with all bits set 31 24 23 Task-State Segment (TSS) 0 11111111 I/O Permission Bit Map Software Interrupt Redirection Bit Map (32 Bytes) I/O base map must not exceed DFFFH. I/O Map Base 64H 0 Figure 16-5. Software Interrupt Redirection Bit Map in TSS Redirecting software interrupts back to the 8086 program potentially speeds up interrupt handling because a switch back and forth between virtual-8086 mode and protected mode is not required. This latter interrupt-handling technique is particularly useful for 8086 operating systems (such as MS-DOS) that use the INT n instruction to call operating system procedures. The CPUID instruction can be used to verify that the virtual mode extension is implemented on the processor. Bit 1 of the feature flags register (EDX) indicates the availability of the virtual mode extension (refer to “CPUID—CPU Identification” in Chapter 3 of the Intel Architecture Software Developer’s Manual, Volume 2). The following sections describe the six methods (or mechanisms) for handling software interrupts in virtual-8086 mode. Refer to Section 16.3.2., “Class 2—Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism” for a description of the use of the VIF and VIP flags in the EFLAGS register for handling maskable hardware interrupts. 188.8.131.52. METHOD 1: SOFTWARE INTERRUPT HANDLING When the VME flag in control register CR4 is clear and the IOPL field is 3, a Pentium®, or P6family processor handles software...
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