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Unformatted text preview: event will be counted twice (if the stalled instruction comes on the next clock after the multiply) or by one (if the stalled instruction comes two clocks after the multiply). Comments 37H 37H Number of predicted returns (whether they are predicted correctly and incorrectly. Number of clocks the pipe is stalled since the destination of previous MMX™ multiply instruction is not ready yet. 38H 38H MOVD/MOVQ_ STORE_STALL_ DUE_TO_ PREVIOUS_MMX_ OPERATION (Counter 1) RETURNS (Counter 0) Number of clocks a MOVD/MOVQ instruction store is stalled in D2 stage due to a previous MMX™ operation with a destination to be used in the store instruction. Number or returns executed. Only RET instructions are counted; IRET instructions are not counted. Any exception taken on a RET instruction and any interrupt recognized by the processor on the instruction boundary prior to the execution of the RET instruction will also cause this counter to be incremented. 39H 39H 3AH Reserved BTB_FALSE_ ENTRIES (Counter 0) Number of false entries in the Branch Target Buffer. False entries are causes for misprediction other than a wrong prediction. A-21 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.)
Event Num. 3AH Mnemonic Event Name BTB_MISS_ PREDICTION_ON_ NOT-TAKEN_ BRANCH (Counter 1) FULL_WRITE_ BUFFER_STALL_ DURATION_ WHILE_ EXECUTING_MMX_ INSTRUCTIONS (Counter 0) STALL_ON_MMX_ INSTRUCTION_ WRITE_TO E-_OR_ M-STATE_LINE (Counter 1) Description Number of times the BTB predicted a not-taken branch as taken. Comments 3BH Number of clocks while the pipeline is stalled due to full write buffers while executing MMX™ instructions. 3BH Number of clocks during stalls on MMX™ instructions writing to Eor M-state lines. A-22 B
Model-Specific Registers APPENDIX B MODEL-SPECIFIC REGISTERS
Table B-1 lists the model-specific registers (MSRs) that can be read with the RDMSR and written with the WRMSR instructions. Register addresses are given in both hexadecimal and decimal; the register name is the mnemonic register name; the bit description describes individual bits in registers.
NOTE The registers with addresses 0H, 1H, 10H, 11H, 12H, and 13H in Table B-1 are available only in the Pentium® processor. Code code that accesses registers 0H, 1H, and 10H will run on a P6 family processor without generating exceptions; however, code that accesses registers 11H, 12H, and 13H will generate exceptions on a P6 family processor. The MSRs in this table that are shaded are available only in the Pentium® II and later processors in the P6 family.
Table B-1. Model-Specific Registers (MSRs)
Register Address Hex 0H 1H 10H 11H 12H 13H 1BH Dec 0 1 16 17 18 19 27 Register Name P5_MC_ADDR (Pentium® Processor Only) P5_MC_TYPE (Pentium® Processor Only) TSC CESR (Pentium® Processor Only) CTR0 (Pentium® Processor Only) CTR1 (Pentium® Processor Only) APICBASE 7:0 8 10:9 11 31:12 Reserved Boot Strap Processor indicator Bit. BSP= 1 Reserved APIC Global Enable Bit - Permanent til reset Enabled = 1, Disabled = 0 APIC Base Address Bit Description B-1 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.)
Register Address Hex Dec 63:32 2AH 42 EBL_CR_POWERON 0 1 Reserved1 Data Error Checking Enable 1 = Enabled 0 = Disabled Read/Write Response Error Checking Enable FRCERR Observation Enable 1 = Enabled 0 = Disabled Read/Write AERR# Drive Enable 1 = Enabled 0 = Disabled Read/Write BERR# Enable for initiator bus requests 1 = Enabled 0 = Disabled Read/Write Reserved BERR# Driver Enable for initiator internal errors 1 = Enabled 0 = Disabled Read/Write BINIT# Driver Enable 1 = Enabled 0 = Disabled Read/Write Output Tri-state Enabled 1 = Enabled 0 = Disabled Read Execute BIST 1 = Enabled 0 = Disabled Read AERR# Observation Enabled 1 = Enabled 0 = Disabled Read Reserved Register Name Reserved Bit Description 2 3 4 5 6 7 8 9 10 11 B-2 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.)
Register Address Hex Dec 12 Register Name Bit Description BINIT# Observation Enabled 1 = Enabled 0 = Disabled Read In Order Queue Depth 1=1 0=8 Read 1Mbyte Power on Reset Vector 1 = 1Mbyte 0 = 4Gbytes Read Only FRC Mode Enable 1 = Enabled 0 = Disabled Read Only APIC Cluster ID Read Reserved Symmetric Arbitration ID Read Clock Frequency Ratio Read Reserved Low Power Mode Enable Read/Write Reserved1 Test Control Register Reserved Streaming Buffer Disable Disable LOCK# assertion for split locked access BIOS Update Trigger Register Chunk 0 data register D[63:0]: used to write to and read from the L2 Chunk 1 data register D[63:0]: used to write to and read from the L2 Chunk 2 data register D[63:0]: used to write to and read from the L2 13 14 15 17:16 19:18 21: 20 24:22 25 26 63:27 33H 51 TEST_CTL 29:0 30 31 79H 88 89 8A 121 136 137 138 BIOS_UPDT_TRIG BBL_CR_D0[63:0] BBL_CR_D1[63:0] BBL_CR_D2[63:0] B-3 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.)
Register Address Hex 8BH Dec 139 Register Name BIOS_SIGN/BBL_CR_D3[ 63:0] PERFCTR0 PERFCTR1 MTRRcap BBL_CR_ADDR [63:0] BBL_CR_ADDR [63:32] BBL_CR_ADDR [31:3] BBL_CR_ADDR [2:0] 118 119 280 281 BBL_CR_DECC[63:0] BBL_CR_CTL Address register: used to send specified address (A31A3) to L2 during cache initialization accesses. Reserved, Address bits [35:3] Reserved Set to 0. Data ECC register D[7:0]: used to write ECC and read ECC to/from L2 Control register: used to program L2 comma...
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- Spring '10