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Unformatted text preview: nsions in either of two ways: • Test for the presence of the feature or extension — Software can test for the presence of new flags in the EFLAGS register and control registers. If these flags are reserved (meaning not present in the processor executing the test), an exception is generated. Likewise, software can attempt to execute a new instruction, which results in an invalidopcode exception (#UD) being generated if it is not supported. Execute the CPUID instruction — The CPUID instruction (added to the Intel Architecture in the Pentium® processor) indicates the presence of new features directly. • Refer to Chapter 10, Processor Identification and Feature Determination, in the Intel Architecture Software Developer’s Manual, Volume 1, for detailed information on detecting new processor features and extensions. 18-2 INTEL ARCHITECTURE COMPATIBILITY 18.5. MMX™ TECHNOLOGY
The Pentium® processor with MMX™ technology introduced the MMX™ technology and a set of MMX™ instructions to the Intel Architecture. The MMX™ instructions are summarized in Chapter 6, Instruction Set Summary, in the Intel Architecture Software Developer’s Manual, Volume 1 and are described in detail in Chapter 3 in the Intel Architecture Software Developer’s Manual, Volume 2. The MMX™ technology and MMX™ instructions are also included in the Pentium® II and Pentium® III processors. 18.6. STREAMING SIMD EXTENSIONS
The Pentium® III processor introduced the Streaming SIMD Extensions. This is a set of new instructions added to enhance perfomance of several classes of applications. The Streaming SIMD Extensions are summarized in Chapter 6, Instruction Set Summary, in the Intel Architecture Software Developer’s Manual, Volume 1 and are described in detail in Chapter 3 in the Intel Architecture Software Developer’s Manual, Volume 2. Several of these new instructions operate in the same register space as the MMX™ instructions. When using these instructions, the rules that apply to MMX™ technology programming apply to this subset of the new instructions as well. 18.7. NEW INSTRUCTIONS IN THE PENTIUM® AND LATER INTEL ARCHITECTURE PROCESSORS
Table 18-1 identifies the instructions introduced into the Intel Architecture in the Pentium® and later Intel Architecture processors.
Table 18-1. New Instructions in the Pentium® and Later Intel Architecture Processors
Instruction Streaming SIMD Extensions SYSENTER/SYSEXIT(fast system call) FXSAVE/FXRSTOR(fast save/restore) CMOVcc (conditional move) FCMOVcc (floating-point conditional move) FCOMI (floating-point compare and set EFLAGS) RDPMC (read performance monitoring counters) UD2 (undefined) CPUID Identification Bits EDX, Bit 25 EDX, Bit 11 EDX, Bit 24 EDX, Bit 15 EDX, Bits 0 and 15 EDX, Bits 0 and 15 EAX, Bits 8-11, set to 6H; refer to Note 1 EAX, Bits 8-11, set to 6H Introduced In Pentium® III processor Pentium® II processor Pentium® II processor Pentium® Pro processor 18-3 INTEL ARCHITECTURE COMPATIBILITY Table 18-1. New Instructions in the Pentium® and Later Intel Architecture Processors
Instruction CMPXCHG8B (compare and exchange 8 bytes) CPUID (CPU identification) RDTSC (read time-stamp counter) RDMSR (read model-specific register) WRMSR (write model-specific register) MMX™ Instructions NOTES: 1. The RDPMC instruction was introduced in the P6 family of processors and added to later model Pentium® processors. This instruction is model specific in nature and not architectural. 2. The CPUID instruction is available in all Pentium® and P6 family processors and in later models of the Intel486™ processors. The ability to set and clear the ID flag (bit 21) in the EFLAGS register indicates the availability of the CPUID instruction. CPUID Identification Bits EDX, Bit 8 None; refer to Note 2 EDX, Bit 4 EDX, Bit 5 EDX, Bit 5 EDX, Bit 23 Introduced In Pentium® processor 18-4 INTEL ARCHITECTURE COMPATIBILITY 18.7.1. Instructions Added Prior to the Pentium® Processor
The following instructions were added in the Intel486™ processor: • • • • • • • • • • • • • • • • • • • • BSWAP (byte swap) instruction. XADD (exchange and add) instruction. CMPXCHG (compare and exchange) instruction. ΙNVD (invalidate cache) instruction. WBINVD (write-back and invalidate cache) instruction. INVLPG (invalidate TLB entry) instruction. The following instructions were added in the Intel386™ processor: LSS, LFS, and LGS (load SS, FS, and GS registers). Long-displacement conditional jumps. Single-bit instructions. Bit scan instructions. Double-shift instructions. Byte set on condition instruction. Move with sign/zero extension. Generalized multiply instruction. MOV to and from control registers. MOV to and from test registers (now obsolete). MOV to and from debug registers. RSM (resume from SMM). This instruction was introduced in the Intel386™ SL and Intel486™ SL processors. The following instructions were added in the Intel 387 math coprocessor: FPREM1. FUCOM, FUCOMP, and FUCOMPP. 18.8. OBSOLETE INSTRUCTIONS
The MOV to and f...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10