IntelSoftwareDevelopersManual

Note that a pair of instructions in which the first

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: of paired instructions if the first instruction is longer than 11 bytes or the second instruction is longer than 7 bytes. Prefixes are not counted. On Pentium® processors without MMX™ technology, prefixed instructions are pairable only in the U-pipe. On Pentium® processors with MMX™ technology, instructions with 0FH, 66H or 67H prefixes are also pairable in the V-pipe. For this and the previous rule, stalls at the entrance to the instruction FIFO, on Pentium® processors with MMX™ technology, will prevent pairing. Floating-point instructions are not pairable with MMX™ instructions. INTEGER PAIRING RULES • • 14.5.1.2. Table 14-2 shows the integer instructions that can be paired. The table is divided into two halves: one for the U-pipe and one for the V-pipe. Any instruction in the U-pipe list can be paired with any instruction in the V-pipe list, and vice versa. 14-13 CODE OPTIMIZATION Table 14-2. Pairable Integer Instructions Integer Instruction Pairable in U-Pipe MOV reg, reg MOV reg, mem MOV mem, reg MOV reg, imm MOV mem, imm MOV eax, mem MOV mem, eax Integer Instruction Pairable in V-Pipe MOV reg, reg MOV reg, mem MOV mem, reg MOV reg, imm MOV mem, imm MOV eax, mem MOV m, eax ALU reg, imm ALU mem, imm ALU eax, imm ALU mem, reg ALU reg, mem INC/DEC reg INC/DEC mem LEA reg, mem PUSH reg PUSH imm POP reg NOP SHIFT/ROT by 1 SHIFT by imm TEST reg, r/m TEST acc, imm ALU reg, imm ALU mem, imm ALU eax, imm ALU mem, reg ALU reg, mem INC./DEC reg INC/DEC mem LEA reg, mem TEST reg, r/m PUSH reg PUSH imm POP reg JMP near Jcc near 0F Jcc CALL near NOP TEST acc, imm ALU reg, reg ALU reg, reg NOTES: ALU—Arithmetic or logical instruction such as ADD, SUB, or AND. In general, most simple ALU instructions are pairable. imm—Immediate. reg—Register. mem—Memory location. r/m—Register or memory location. acc—Accumulator (EAX or AX register). General Integer-Instruction Pairability Rules The following are general rules for pairability of integer instructions. These rules summarize the pairing of instructions in Table 14-2. • NP Instructions—The following integer instructions cannot be paired: — The shift and rotate instructions with a shift count in the CL register. — Long-arithmetic instructions, such as MUL and DIV. — Extended instructions, such as RET, ENTER, PUSHA, MOVS, STOS, and LOOPNZ. — Inter-segment instructions, such as PUSH sreg and CALL far. • UV Instructions—The following instructions can be paired when issued to the U- or Vpipes: — Most 8/32 bit ALU operations, such as ADD, INC, and XOR. — All 8/32 bit compare instructions, such as CMP and TEST. — All 8/32 bit stack operations using registers, such as PUSH reg and POP reg. • PU instructions—The following instructions when issued to the U-pipe can be paired with a suitable instruction in the V-Pipe. These instructions never execute in the V-pipe. — Carry and borrow instructions, such as ADC and SBB. 14-14 CODE OPTIMIZATION — Prefixed instructions. — Shift with immediate instructions. • PV instructions—The following instructions when issued to the V-pipe can be paired with a suitable instruction in the U-Pipe. The simple control transfer instructions, such as the CALL near, JMP near, or Jcc instructions, can execute in either the U-pipe or the V-pipe, but they can be paired with other instructions only when they are in the V-pipe. Since these instructions change the instruction pointer (EIP), they cannot pair in the U-pipe since the next instruction may not be adjacent. The PV instructions include both Jcc short and Jcc near (which have a 0FH prefix) versions of the Jcc instruction. Unpairability Due to Register Dependencies Instruction pairing is also affected by instruction operands. The following instruction pairings will not result in parallel execution because of register contention. Exceptions to these rules are given in “Special Pairs”, in Section 14.5.1.2., “Integer Pairing Rules”. • Flow Dependence—The first instruction writes to a register that the second one reads from, as in the following example: mov mov eax, 8 [ebp], eax • Output Dependence—Both instructions write to the same register, as in the following example. mov mov eax, 8 eax, [ebp] This output dependence limitation does not apply to a pair of instructions that write to the EFLAGS register (for example, two ALU operations that change the condition codes). The condition code after the paired instructions execute will have the condition from the V-pipe instruction. Note that a pair of instructions in which the first reads a register and the second writes to the same register (anti-dependence) may be paired, as in the following example: mov mov eax, ebx ebx, [ebp] For purposes of determining register contention, a reference to a byte or word register is treated as a reference to the containing 32-bit register. Therefore, the following instruction pair does not execute in parallel because of output dependencies on the contents of the EAX register. mov mov al, 1 ah, 0 14-15 CODE OPTIMIZATION Special Pairs Some integer instructions can be pai...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

Ask a homework question - tutors are online