IntelSoftwareDevelopersManual

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Unformatted text preview: h interrupts are disabled. Number of processor cycles for which interrupts are disabled and interrupts are pending. Number of branch instructions retired. Number of mispredicted branches retired. Number of taken branches retired. Number of taken mispredictions branches retired. Number of branch instructions decoded. Number of branches for which the BTB did not produce a prediction. Number of bogus branches. Number of times BACLEAR is asserted. This is the number of times that a static branch prediction was made, in which the branch decoder decided to make a branch prediction because the BTB did not. Counters 0 and 1. Pentium® III processor only. 00H 01H D9H EMON_KNI_COMP_ INST_RET 00H 01H Interrupts C8H C6H C7H HW_INT_RX CYCLES_INT_ MASKED CYCLES_INT_ PENDING_ AND_MASKED BR_INST_RETIRED BR_MISS_PRED_ RETIRED BR_TAKEN_ RETIRED BR_MISS_PRED_ TAKEN_RET BR_INST_DECODED BTB_MISSES 00H 00H 00H Counters 0 and 1. Pentium® III processor only. Branches C4H C5H C9H CAH E0H E2H 00H 00H 00H 00H 00H 00H E4H E6H BR_BOGUS BACLEARS 00H 00H A-9 PERFORMANCE-MONITORING EVENTS Table A-1. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.) Unit Stalls Event Num. A2H Mnemonic Event Name RESOURCE_STALLS Unit Mask 00H Description Incremented by 1 during every cycle for which there is a resource related stall. Includes register renaming buffer entries, memory buffer entries. Does not include stalls due to bus queue full, too many cache misses, etc. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations. Comments D2H PARTIAL_RAT_ STALLS 00H Number of cycles or events for partial stalls. Note: Includes flag partial stalls. Segment Register Loads Clocks MMX™ Unit 06H SEGMENT_REG_ LOADS CPU_CLK_ UNHALTED MMX_INSTR_EXEC 00H Number of segment register loads. Number of cycles during which the processor is not halted. Number of MMX™ Instructions Executed. Available in Intel® Celeron™, Pentium® II and Pentium® II Xeon™ processors only. Does not account for MOVQ and MOVD stores from register to memory. 79H B0H 00H 00H B1H MMX_SAT_ INSTR_EXEC 00H Number of MMX™ Saturating Instructions Executed. Available in Pentium® II & Pentium® III processors only. Available in Pentium® II & Pentium® III processors only. Available in Pentium® II & Pentium® III processors only. B2H MMX_UOPS_EXEC 0FH Number of MMX™ UOPS Executed. MMX™ packed multiply instructions executed. MMX™ packed shift instructions executed. MMX™ pack operation instructions executed. MMX™ unpack operation instructions executed. MMX™ packed logical instructions executed. MMX™ packed arithmetic instructions executed. B3H MMX_INSTR_ TYPE_EXEC 01H 02H 04H 08H 10H 20H A-10 PERFORMANCE-MONITORING EVENTS Table A-1. Events That Can Be Counted with the P6 Family PerformanceMonitoring Counters (Contd.) Unit Event Num. CCH Mnemonic Event Name FP_MMX_TRANS Unit Mask 00H 01H Description Transitions from MMX™ instruction to floating-point instructions. Transitions from floating-point instructions to MMX ™ instructions. Number of MMX™ Assists (that is, the number of EMMS instructions executed). Number of MMX™ Instructions Retired. Number of Segment Register Renaming Stalls: Segment register ES Segment register DS Segment register FS Segment register FS Segment registers ES + DS + FS + GS Number of Segment Register Renames: Segment register ES Segment register DS Segment register FS Segment register FS Segment registers ES + DS + FS + GS Number of segment register rename events retired. Comments Available in Pentium® II & Pentium® III processors only. CDH MMX_ASSIST 00H Available in Pentium® II & Pentium® III processors only. Available in Pentium® II processor only. Available in Pentium® II & Pentium® III processors only. CEH Segment Register Renaming D4H MMX_INSTR_RET SEG_RENAME_ STALLS 00H 01H 02H 04H 08H 0FH D5H SEG_REG_ RENAMES 01H 02H 04H 08H 0FH D6H RET_SEG_ RENAMES 00H Available in Pentium® II & Pentium® III processors only. Available in Pentium® II & Pentium® III processors only. NOTES: 1. Several L2 cache events, where noted, can be further qualified using the Unit Mask (UMSK) field in the PerfEvtSel0 and PerfEvtSel1 registers. The lower 4 bits of the Unit Mask field are used in conjunction with L2 events to indicate the cache state or cache states involved. The P6 family processors identify cache states using the “MESI” protocol and consequently each bit in the Unit Mask field represents one of the four states: UMSK[3] = M (8H) state, UMSK[2] = E (4H) state, UMSK[1] = S (2H) state, and UMSK[0] = I (1H) state. UMSK[3:0] = MESI” (FH) should be used to collect data for all states; UMSK = 0H, for the applicable events, will result in nothing being counted. 2. All of the external bus logic (...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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