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Number of times d1 stage cannot issue any

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Unformatted text preview: the execute stage of either of U- or Vpipelines is writing to either the index or base address register of an instruction in the D2 (address generation) stage of either the U- or V- pipelines. 20H 21H 22H Reserved Reserved FLOPS Number of floating-point operations that occur. Number of floating-point adds, subtracts, multiplies, divides, remainders, and square roots are counted. The transcendental instructions consist of multiple adds and multiplies and will signal this event multiple times. Instructions generating the divide-by-zero, negative square root, special operand, or stack exceptions will not be counted. Instructions generating all other floating-point exceptions will be counted. The integer multiply instructions and other instructions which use the FPU will be counted. A-16 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.) Event Num. 23H Mnemonic Event Name BREAKPOINT MATCH ON DR0 REGISTER Description Number of matches on register DR0 breakpoint. Comments The counters is incremented regardless if the breakpoints are enabled or not. However, if breakpoints are not enabled, code breakpoint matches will not be checked for instructions executed in the V-pipe and will not cause this counter to be incremented. (They are checked on instruction executed in the U-pipe only when breakpoints are not enabled.) These events correspond to the signals driven on the BP[3:0] pins. Refer to Chapter 15, Debugging and Performance Monitoring, for more information. Refer to comment for 23H event. 24H BREAKPOINT MATCH ON DR1 REGISTER BREAKPOINT MATCH ON DR2 REGISTER BREAKPOINT MATCH ON DR3 REGISTER HARDWARE INTERRUPTS DATA_READ_OR_ WRITE Number of matches on register DR1 breakpoint. Number of matches on register DR2 breakpoint. Number of matches on register DR3 breakpoint. Number of taken INTR and NMI interrupts. Number of memory data reads and/or writes (internal data cache hit and miss combined). 25H Refer to comment for 23H event. 26H Refer to comment for 23H event. 27H 28H Split cycle reads and writes are counted individually. Data Memory Reads that are part of TLB miss processing are not included. These events may occur at a maximum of two per clock. I/O is not included. Additional reads to the same cache line after the first BRDY# of the burst line fill is returned but before the final (fourth) BRDY# has been returned, will not cause the counter to be incremented additional times. Data accesses that are part of TLB miss processing are not included. Accesses directed to I/O space are not included. 29H DATA_READ_MISS OR_WRITE MISS Number of memory read and/or write accesses that miss the internal data cache whether or not the access is cacheable or noncacheable. A-17 PERFORMANCE-MONITORING EVENTS Table A-2. Events That Can Be Counted with the Pentium® Processor PerformanceMonitoring Counters (Contd.) Event Num. 2AH Mnemonic Event Name BUS_OWNERSHIP_ LATENCY (Counter 0) Description The time from LRM bus ownership request to bus ownership granted (that is, the time from the earlier of a PBREQ (0), PHITM# or HITM# assertion to a PBGNT assertion). The number of buss ownership transfers (that is, the number of PBREQ (0) assertions. Number of MMX™ instructions executed in the U-pipe. Number of MMX™ instructions executed in the V-pipe. Number of times a processor identified a hit to a modified line due to a memory access in the other processor (PHITM (O)). Number of shared data lines in the L1 cache (PHIT (O)). Number of EMMS instructions executed. If the average memory latencies of the system are known, this event enables the user to count the Write Backs on PHITM(O) penalty and the Latency on Hit Modified(I) penalty. Comments The ratio of the 2AH events counted on counter 0 and counter 1 is the average stall time due to bus ownership conflict. 2AH BUS OWNERSHIP TRANSFERS (Counter 1) MMX_ INSTRUCTIONS_ EXECUTED_ U-PIPE (Counter 0) MMX_ INSTRUCTIONS_ EXECUTED_ V-PIPE (Counter 1) CACHE_MSTATE_LINE_ SHARING (Counter 0) The ratio of the 2AH events counted on counter 0 and counter 1 is the average stall time due to bus ownership conflict. 2BH 2BH 2CH 2CH CACHE_LINE_ SHARING (Counter 1) EMMS_ INSTRUCTIONS_ EXECUTED (Counter 0) TRANSITIONS_ BETWEEN_MMX_ AND_FP_ INSTRUCTIONS (Counter 1) 2DH 2DH Number of transitions between MMX™ and floating-point instructions or vice versa. An even count indicates the processor is in MMX™ state. an odd count indicates it is in FP state. Number of clocks the bus is busy due to the processor’s own activity, i.e., the bus activity that is caused by the processor. This event counts the first floating-point instruction following an MMX™ instruction or first MMX™ instruction following a floating-point instruction. The count may be used to estimate the penalty in transitions between floatingpoint state and MMX™ state. 2DH BUS_UTILIZATION_ DUE_TO_ PROCESSOR_ ACTIVITY (Counter 0) A-18 PERFORMANCE-MONITORING EVENTS Table A-2....
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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