Numeric error bit 5 of cr0 enables the native internal

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ic alignment checking when set; disables alignment checking when clear. Alignment checking is performed only when the AM flag is set, the AC flag in the EFLAGS register is set, the CPL is 3, and the processor is operating in either protected or virtual-8086 mode. Write Protect (bit 16 of CR0). Inhibits supervisor-level procedures from writing into user-level read-only pages when set; allows supervisor-level procedures to write into user-level read-only pages when clear. This flag facilitates implementation of the copyon-write method of creating a new process (forking) used by operating systems such as UNIX*. Numeric Error (bit 5 of CR0). Enables the native (internal) mechanism for reporting FPU errors when set; enables the PC-style FPU error reporting mechanism when clear. When the NE flag is clear and the IGNNE# input is asserted, FPU errors are ignored. When the NE flag is clear and the IGNNE# input is deasserted, an unmasked FPU error causes the processor to assert the FERR# pin to generate an external interrupt and to stop instruction execution immediately before executing the next waiting floatingpoint instruction or WAIT/FWAIT instruction. The FERR# pin is intended to drive an input to an external interrupt controller (the FERR# pin emulates the ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors). The NE flag, IGNNE# pin, and FERR# pin are used with external logic to implement PC-style error reporting. (Refer to “Software Exception Handling” in Chapter 7, and Appendix D in the Intel Architecture Software Developer’s Manual, Volume 1, for more information about FPU error reporting and for detailed information on when the FERR# pin is asserted, which is implementation dependent.) Extension Type (bit 4 of CR0). Reserved in the P6 family and Pentium® processors. (In the P6 family processors, this flag is hardcoded to 1.) In the Intel386™ and Intel486™ processors, this flag indicates support of Intel 387 DX math coprocessor instructions when set. Task Switched (bit 3 of CR0). Allows the saving of FPU context on a task switch to be delayed until the FPU is actually accessed by the new task. The processor sets this flag on every task switch and tests it when interpreting floating-point arithmetic instructions. WP NE ET TS • • If the TS flag is set, a device-not-available exception (#NM) is raised prior to the execution of a floating-point instruction. If the TS flag and the MP flag (also in the CR0 register) are both set, an #NM exception is raised prior to the execution of floating-point instruction or a WAIT/FWAIT instruction. Table 2-1 shows the actions taken for floating-point, WAIT/FWAIT, MMX™, and Streaming SIMD Extensions based on the settings of the TS, EM, and MP flags. 2-14 SYSTEM ARCHITECTURE OVERVIEW Table 2-1. Action Taken for Combinations of EM, MP, TS, CR4.OSFXSR, and CPUID.XMM CR0 Flags EM MP TS CR4 OSFXSR CPUID XMM Floating-Point Instruction Type WAIT/FWAIT MMX™ Technology Execute #NM Exception Execute #NM Exception #UD Exception #UD Exception #UD Exception MMX™ Technology #UD Exception Streaming SIMD Extensions Streaming SIMD Extensions #UD Interrupt 6 #NM Interrupt 7 #UD Interrupt 6 #UD Interrupt 6 0 0 0 0 1 1 1 EM 0 0 1 1 0 0 1 MP 0 1 0 1 0 1 0 TS OSFXSR XMM Execute #NM Exception Execute #NM Exception #NM Exception #NM Exception #NM Exception Floating-Point Execute Execute Execute #NM Exception Execute Execute Execute WAIT/FWAIT 1 1 0 - 1 - 1 1 - 1 0 - 1 0 #NM Exception - #NM Exception - The processor does not automatically save the context of the FPU on a task switch. Instead it sets the TS flag, which causes the processor to raise an #NM exception whenever it encounters a floating-point instruction in the instruction stream for the new task. The fault handler for the #NM exception can then be used to clear the TS flag (with the CLTS instruction) and save the context of the FPU. If the task never encounters a floating-point instruction, the FPU context is never saved. EM Emulation (bit 2 of CR0). Indicates that the processor does not have an internal or external FPU when set; indicates an FPU is present when clear. When the EM flag is set, execution of a floating-point instruction generates a device-not-available exception (#NM). This flag must be set when the processor does not have an internal FPU or is not connected to a math coprocessor. If the processor does have an internal FPU, setting this flag would force all floating-point instructions to be handled by software emulation. Table 8-2 in Chapter 8, Processor Management and Initialization shows the recommended setting of this flag, depending on the Intel Architecture processor and 2-15 SYSTEM ARCHITECTURE OVERVIEW FPU or math coprocessor present in the system. Table 2-1 shows the interaction of the EM, MP, and TS flags. Note that the EM flag also affects the execution of the MMX™ instructions (refer to Table 2-1). When this flag is set, execution of an MMX™ instruction causes an invalid opcode e...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online