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Unformatted text preview: les reporting of the associated error and clearing it disables reporting of the error. Writing the 64-bit value FFFFFFFFFFFFFFFFH to an MCi_CTL register enables logging of all errors. The processor does not write changes to bits that are not implemented. Figure 13-4 shows the bit fields of MCi_CTL
NOTE Operating system or executive software must not modify the contents of the MC0_CTL register. The MC0_CTL register is internally aliased to the EBL_CR_POWERON register and as such controls system-specific error handling features. These features are platform specific. System specific firmware (the BIOS) is responsible for the appropriate initialization of MC0_CTL. The P6 family processors only allows the writing of all 1s or all 0s to the MCi_CTL registers. 63 62 61
E E 6 3 E E 6 2 E E 6 1 .....
EEj—Error reporting enable flag (where j is 00 through 63) 3210
E E 0 2 EE EE 00 10 Figure 13-4. MCi_CTL Register 13-4 MACHINE-CHECK ARCHITECTURE 220.127.116.11. MCi_STATUS MSR The MCi_STATUS MSR contains information related to a machine-check error if its VAL (valid) flag is set (refer to Figure 13-5). Software is responsible for clearing the MC i_STATUS register by writing it with all 0s; writing 1s to this register will cause a general-protection exception to be generated. The flags and fields in this register are as follows: MCA (machine-check architecture) error code field, bits 0 through 15 Specifies the machine-check architecture-defined error code for the machine-check error condition detected. The machine-check architecture-defined error codes are guaranteed to be the same for all Intel Architecture processors that implement the machine-check architecture. Refer to Section 13.6., “Interpreting the MCA Error Codes” for information on machine-check error codes. 63 62 6160 59 58 5756
V UE AOCN L P C C 32 31 16 15 0 Other Information Model-Specific Error Code MCA Error Code PCC—Processor context corrupt ADDRV—MCi_ADDR register valid MISCV—MCi_MISC register valid EN—Error enabled UC—Uncorrected error OVER—Error overflow VAL—MCi_STATUS register valid Figure 13-5. MCi_STATUS Register Model-specific error code field, bits 16 through 31 Specifies the model-specific error code that uniquely identifies the machine-check error condition detected. The model-specific error codes may differ among Intel Architecture processors for the same machine-check error condition. Other information field, bits 32 through 56 The functions of the bits in this field are implementation specific and are not part of the machine-check architecture. Software that is intended to be portable among Intel Architecture processors should not rely on the values in this field. PCC (processor context corrupt) flag, bit 57 Indicates (when set) that the state of the processor might have been corrupted by the error condition detected and that reliable restarting of the processor may not be possible. When clear, this flag indicates that the error did not affect the processor’s state. ADDRV (MCi_ADDR register valid) flag, bit 58 Indicates (when set) that the MCi_ADDR register contains the address where the error occurred (refer to Section 18.104.22.168., “MCi_ADDR MSR”). When clear, this flag indicates that the MCi_ADDR register does not contain the address where the error occurred. Do not read these registers if they are not implemented in the processor. 13-5 MACHINE-CHECK ARCHITECTURE MISCV (MCi_MISC register valid) flag, bit 59 Indicates (when set) that the MCi_MISC register contains additional information regarding the error. When clear, this flag indicates that the MCi_MISC register does not contain additional information regarding the error. Do not read these registers if they are not implemented in the processor EN (error enabled) flag, bit 60 Indicates (when set) that the error was enabled by the associated EEj bit of the MCi_CTL register. UC (error uncorrected) flag, bit 61 Indicates (when set) that the processor did not or was not able to correct the error condition. When clear, this flag indicates that the processor was able to correct the error condition. OVER (machine check overflow) flag, bit 62 Indicates (when set) that a machine-check error occurred while the results of a previous error were still in the error-reporting register bank (that is, the VAL bit was already set in the MCi_STATUS register). The processor sets the OVER flag and software is responsible for clearing it. Enabled errors are written over disabled errors, and uncorrected errors are written over corrected errors. Uncorrected errors are not written over previous valid uncorrected errors. VAL (MCi_STATUS register valid) flag, bit 63 Indicates (when set) that the information within the MCi_STATUS register is valid. When this flag is set, the processor follows the rules given for the OVER flag in the MCi_STATUS register when overwriting previously valid entries. The processor sets the VAL flag and software is responsible for clearing it. 22.214.171.124. MCi_ADDR MSR The MCi_ADDR MSR contains the address of the code or data memory location that produced the machine-check error if the ADDRV flag in the MCi_...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10