Unformatted text preview: rom test registers instructions were removed from the Pentium® and future Intel Architecture processors. Execution of these instructions generates an invalid-opcode exception (#UD). 18-5 INTEL ARCHITECTURE COMPATIBILITY 18.9. UNDEFINED OPCODES
All new instructions defined for Intel Architecture processors use binary encodings that were reserved on earlier-generation processors. Attempting to execute a reserved opcode always results in an invalid-opcode (#UD) exception being generated. Consequently, programs that execute correctly on earlier-generation processors cannot erroneously execute these instructions and thereby produce unexpected results when executed on later Intel Architecture processors. 18.10.NEW FLAGS IN THE EFLAGS REGISTER
The section titled “EFLAGS Register” in Chapter 3 of the Intel Architecture Software Developer’s Manual, Volume 1, shows the configuration of flags in the EFLAGS register for the P6 family processors. No new flags have been added to this register in the P6 family processors. The flags added to this register in the Pentium® and Intel486™ processors are described in the following sections. The following flags were added to the EFLAGS register in the Pentium® processor: • • • VIF (virtual interrupt flag), bit 19. VIP (virtual interrupt pending), bit 20. ID (identification flag), bit 21. The AC flag (bit 18) was added to the EFLAGS register in the Intel486™ processor. 18.10.1. Using EFLAGS Flags to Distinguish Between 32-Bit Intel Architecture Processors
The following bits in the EFLAGS register that can be used to differentiate between the 32-bit Intel Architecture processors: • • • Bit 18 (the AC flag) can be used to distinguish an Intel386™ processor from the P6 family, Pentium®, and Intel486™ processors. Since it is not implemented on the Intel386™ processor, it will always be clear. Bit 21 (the ID flag) indicates whether an application can execute the CPUID instruction. The ability to set and clear this bit indicates that the processor is a P6 family or Pentium® processor. The CPUID instruction can then be used to determine which processor. Bits 19 (the VIF flag) and 20 (the VIP flag) will always be zero on processors that do not support virtual mode extensions, which includes all 32-bit processors prior to the Pentium® processor. Refer to Chapter 10, Processor Identification and Feature Determination, in the Intel Architecture Software Developer’s Manual, Volume 1, for more information on identifying processors. 18-6 INTEL ARCHITECTURE COMPATIBILITY 18.11.STACK OPERATIONS
This section identifies the differences in stack implementation between the various Intel Architecture processors. 18.11.1. PUSH SP
The P6 family, Pentium®, Intel486™, Intel386™, and Intel 286 processors push a different value on the stack for a PUSH SP instruction than the 8086 processor. The 32-bit processors push the value of the SP register before it is decremented as part of the push operation; the 8086 processor pushes the value of the SP register after it is decremented. If the value pushed is important, replace PUSH SP instructions with the following three instructions:
PUSH BP MOV BP, SP XCHG BP, [BP] This code functions as the 8086 processor PUSH SP instruction on the P6 family, Pentium®, Intel486™, Intel386™, and Intel 286 processors. 18.11.2. EFLAGS Pushed on the Stack
The setting of the stored values of bits 12 through 15 (which includes the IOPL field and the NT flag) in the EFLAGS register by the PUSHF instruction, by interrupts, and by exceptions is different with the 32-bit Intel Architecture processors than with the 8086 and Intel 286 processors. The differences are as follows: • • • 8086 processor—bits 12 through 15 are always set. Intel 286 processor—bits 12 through 15 are always cleared in real-address mode. 32-bit processors in real-address mode—bit 15 (reserved) is always cleared, and bits 12 through 14 have the last value loaded into them. 18.12.FPU
This section addresses the issues that must be faced when porting floating-point software designed to run on earlier Intel Architecture processors and math coprocessors to a Pentium® or P6 family processor with integrated FPU. To software, a P6 family processor looks very much like a Pentium® processor. Floating-point software which runs on a Pentium® or Intel486™ DX processor, or on an Intel486™ SX processor/Intel 487 SX math coprocessor system or an Intel386™ processor/Intel 387 math coprocessor system, will run with at most minor modifications on a P6 family processor. To port code directly from an Intel 286 processor/Intel 287 math coprocessor system or an Intel 8086 processor/8087 math coprocessor system to the Pentium® and P6 family processors, certain additional issues must be addressed. 18-7 INTEL ARCHITECTURE COMPATIBILITY In the following sections, the term “32-bit Intel Architecture FPUs” refers to the P6 family, Pentium®, and Intel486™ DX processors, and to the Intel 487 SX and Intel 387 math coprocessors; the term “16-bit Intel Architecture math coprocessors” refers to the Intel 287 and 8087 math coprocessors. 18...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10