On power up or reset of the processor the base

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Unformatted text preview: ddress specifies the linear address of byte 0 of the TSS; the segment limit specifies the number of bytes in the TSS. (Refer to Section 6.2.3., “Task Register” in Chapter 6, Task Management for more information about the task register.) The LTR and STR instructions load and store the segment selector part of the task register, respectively. When the LTR instruction loads a segment selector in the task register, the base 2-11 SYSTEM ARCHITECTURE OVERVIEW address, limit, and descriptor attributes from the TSS descriptor are automatically loaded into the task register. On power up or reset of the processor, the base address is set to the default value of 0 and the limit is set to FFFFH. When a task switch occurs, the task register is automatically loaded with the segment selector and descriptor for the TSS for the new task. The contents of the task register are not automatically saved prior to writing the new TSS information into the register. 2.5. CONTROL REGISTERS The control registers (CR0, CR1, CR2, CR3, and CR4) determine operating mode of the processor and the characteristics of the currently executing task (refer to Figure 2-5). 31 10 9876543210 TPV PPMPP CGCASDSVM ED I E EEEEE Reserved (set to 0) CR4 OSXMMEXCPT OSFXSR 31 12 11 5432 PP CW DT 0 0 Page-Directory Base 31 CR3 (PDBR) Page-Fault Linear Address 31 0 CR2 CR1 31 30 29 30 PCN GDW 19 18 17 16 15 A M W P 6543210 NE TEMP ETSMPE CR0 Reserved Figure 2-5. Control Registers 2-12 SYSTEM ARCHITECTURE OVERVIEW The control registers: • • • • CR0—Contains system control flags that control operating mode and states of the processor. CR1—Reserved. CR2—Contains the page-fault linear address (the linear address that caused a page fault). CR3—Contains the physical address of the base of the page directory and two flags (PCD and PWT). This register is also known as the page-directory base register (PDBR). Only the 20 most-significant bits of the page-directory base address are specified; the lower 12 bits of the address are assumed to be 0. The page directory must thus be aligned to a page (4-KByte) boundary. The PCD and PWT flags control caching of the page directory in the processor’s internal data caches (they do not control TLB caching of page-directory information). When using the physical address extension, the CR3 register contains the base address of the page-directory-pointer table (refer to Section 3.8., “Physical Address Extension” in Chapter 3, Protected-Mode Memory Management). • CR4—Contains a group of flags that enable several architectural extensions, as well as indicating the level of OS support for the Streaming SIMD Extensions. In protected mode, the move-to-or-from-control-registers forms of the MOV instruction allow the control registers to be read (at privilege level 0 only) or loaded (at privilege level 0 only). These restrictions mean that application programs (running at privilege levels 1, 2, or 3) are prevented from reading or loading the control registers. A program running at privilege level 1, 2, or 3 should not attempt to read or write the control registers. An attempt to read or write these registers will result in a general protection fault (GP(0)). The functions of the flags in the control registers are as follows: PG Paging (bit 31 of CR0). Enables paging when set; disables paging when clear. When paging is disabled, all linear addresses are treated as physical addresses. The PG flag has no effect if the PE flag (bit 0 of register CR0) is not also set; in fact, setting the PG flag when the PE flag is clear causes a general-protection exception (#GP) to be generated. Refer to Section 3.6., “Paging (Virtual Memory)” in Chapter 3, Protected-Mode Memory Management for a detailed description of the processor’s paging mechanism. Cache Disable (bit 30 of CR0). When the CD and NW flags are clear, caching of memory locations for the whole of physical memory in the processor’s internal (and external) caches is enabled. When the CD flag is set, caching is restricted as described in Table 9-4, in Chapter 9, Memory Cache Control. To prevent the processor from accessing and updating its caches, the CD flag must be set and the caches must be invalidated so that no cache hits can occur (refer to Section 9.5.2., “Preventing Caching”, in Chapter 9, Memory Cache Control). Refer to Section 9.5., “Cache Control”, Chapter 9, Memory Cache Control, for a detailed description of the additional restrictions that can be placed on the caching of selected pages or regions of memory. Not Write-through (bit 29 of CR0). When the NW and CD flags are clear, write-back (for Pentium® and P6 family processors) or write-through (for Intel486™ processors) is enabled for writes that hit the cache and invalidation cycles are enabled. Refer to 2-13 CD NW SYSTEM ARCHITECTURE OVERVIEW Table 9-4, in Chapter 9, Memory Cache Control, for detailed information about the affect of the NW flag on caching for other settings of the CD and NW flags. AM Alignment Mask (bit 18 of CR0). Enables automat...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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