IntelSoftwareDevelopersManual

Pcd 0 0 1 1 0 0 1 1 pwt 0 1 0 1 0 1 0 1 pat entry 0 1

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Unformatted text preview: eature is detected by an operating system through the use of the CPUID instruction. Specifically, the operating system executes the CPUID instruction with the value 1 in the EAX register, and then determines support for the feature by inspecting bit 16 of the EDX register return value. If the PAT is supported, an operating system is permitted to utilize the model specific register (MSR) specified for programming the PAT, as well as make use of the PAT-index bit (PATi), which was formerly a reserved bit in the page tables. Note that there is not a separate flag or control bit in any of the control registers that enables the use of this feature. The PAT is always enabled on all processors that support it, and the table lookup always occurs whenever paging is enabled and for all paging modes (e.g., PSE, PAE). 9.13.3. Technical Description of the PAT The Page Attribute Table is a Model Specific Register (MSR) at address 277H (for information about the MSRs, refer to Appendix B, Model-Specific Registers. The model specific register address for the PAT is defined and will remain at the same address on future Intel processors that support this feature. Figure 9-7 shows the format of the 64-bit register containing the PAT. 31 Rsvd 27 26 PA3 24 23 Rsvd 19 18 PA 2 16 15 Rsvd 11 10 PA 1 8 7 Rsvd 3 2 PA 0 0 63 Rsvd 59 58 PA7 56 55 Rsvd 51 50 PA6 48 47 Rsvd 43 42 PA5 40 39 Rsvd 35 34 PA4 32 NOTES: 1. PA0-7 = Specifies the eight page attribute locations contained within the PAT 2. Rsvd = Most significant bits for each Page Attribute are reserved for future expansion Figure 9-7. Page Attribute Table Model Specific Register Each of the eight page attribute fields can contain any of the available memory type encodings, or indexes, as specified in Table 9-1. 9-34 MEMORY CACHE CONTROL 9.13.4. Accessing the PAT Access to the memory types that have been programmed into the PAT register fields is accomplished with a 3-bit index consisting of the PATi, PCD, and PWT bits. Table 9-8 shows how the PAT register fields are indexed. The last column of the table shows which memory type the processor assigns to each PAT field at processor reset and initialization. These initial values provide complete backward compatibility with previous Intel processors and existing software that use the previously existing page-table memory types and MTRRs. Table 9-8. PAT Indexing and Values After Reset PATi 0 0 0 0 1 1 1 1 NOTES: 1. PATi bit is defined as bit 7 for 4 KB PTEs, bit 12 for PDEs mapping 2 MB/4 MB pages. 2. UC- is the page encoding PCD, PWT = 10 on P6 family processors that do not support this feature. UCin the page table is overridden by WC in the MTRRs. 3. UC is the page encoding PCD, PWT = 11 on P6 family processors that do not support this feature. UC in the page-table overrides WC in the MTRRs. 1 PCD 0 0 1 1 0 0 1 1 PWT 0 1 0 1 0 1 0 1 PAT Entry 0 1 2 3 4 5 6 7 Memory Type at Reset WB WT UC-2 UC3 WB WT UC-2 UC3 In P6 family processors that do not support the PAT, the PCD and PWT bits are used to determine the page-table memory types of a given physical page. The PAT feature redefines these two bits and combines them with a newly defined PAT-index bit (PATi) in the page-directory and page-table entries. These three bits create an index into the 8-entry Page Attribute Table. The memory type from the PAT is used in place of PCD and PWT for computing the effective memory type. The bit used for PATi differs depending upon the level of the paging hierarchy. PATi is bit 7 for page-table entries, and bit 12 for page-directory entries that map to large pages. Reserved bit faults are disabled for nonzero values for PATi, but remain present for all other reserved bits. This is true for 4 KB/2 MB pages when PAE is enabled. The PAT index scheme for each level of the paging hierarchy is shown in Figure 9-8. 9-35 MEMORY CACHE CONTROL 31 4 3 PCD PWT Page-Directory Base Register (CR3) 31 4 3 PCD and PWT provide 2 bit index into the PAT, allowing use of first 4 entries PCD PWT Page-Directory Pointer Table Entry 31 4 3 PCD PWT 4 KB Page-Directory Entry 31 13 12 PATi 4 PCD 3 PWT PATi, PCD, and PWT provide 3 bit index into the PAT, allowing use of all 8 entries 2 MB/4 MB Page-Directory Entry 31 8 7 PATi 4 PCD 3 PWT 4 KB Page-Table Entry Figure 9-8. Page Attribute Table Index Scheme for Paging Hierarchy NOTE: This figure only shows the format of the lower 32 bits of the PDE, PDEPTR, and PTEs when in PAE mode Refer to Figure 3-21 from Chapter 3, Protected-Mode Memory Management of the Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide. Additionally, the formats shown in this figure are not meant to accurately represent the entire structure, but only the labeled bits. Figure 9-8 shows that the PAT bit is not defined in CR3, the Page-Directory-Pointer Tables when PAE is enabled, or the Page Directory when it doesn’t describe a large page. In these cases, only PCD and PWT are used to index into the PAT, limiting the operating system to using only the first 4 entries of PAT for describing the...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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