IntelSoftwareDevelopersManual

Pointer entry 32 cr3 pdbr 32 bits aligned onto a 32

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ess translation is changed to allow mapping 32-bit linear addresses into the larger physical address space. 31 0 • • Page-Directory-Pointer-Table Base Address PP CW0 0 0 DT Figure 3-17. Register CR3 Format When the Physical Address Extension is Enabled 3.8.1. Linear Address Translation With Extended Addressing Enabled (4-KByte Pages) Figure 3-12 shows the page-directory-pointer, page-directory, and page-table hierarchy when mapping linear addresses to 4-KByte pages with extended physical addressing enabled. This paging method can be used to address up to 220 pages, which spans a linear address space of 232 bytes (4 GBytes). 3-30 PROTECTED-MODE MEMORY MANAGEMENT Directory Pointer Linear Address 31 30 29 21 20 12 11 Table Directory 0 Offset 12 4-KByte Page Physical Address Page Table Page Directory 9 2 Directory Entry Page-Table Entry 9 Page-DirectoryPointer Table 4 PDPTE ∗ 512 PDE ∗ 512 PTE = 220 Pages Dir. Pointer Entry 32* CR3 (PDBR) *32 bits aligned onto a 32-byte boundary Figure 3-18. Linear Address Translation With Extended Physical Addressing Enabled (4-KByte Pages) To select the various table entries, the linear address is divided into three sections: • • • • Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to one of the 4 entries in the page-directory-pointer table. The selected entry provides the base physical address of a page directory. Page-directory entry—Bits 21 through 29 provide an offset to an entry in the selected page directory. The selected entry provides the base physical address of a page table. Page-table entry—Bits 12 through 20 provide an offset to an entry in the selected page table. This entry provides the base physical address of a page in physical memory. Page offset—Bits 0 through 11 provide an offset to a physical address in the page. 3-31 PROTECTED-MODE MEMORY MANAGEMENT 3.8.2. Linear Address Translation With Extended Addressing Enabled (2-MByte or 4-MByte Pages) Figure 3-12 shows how a page-directory-pointer table and page directories can be used to map linear addresses to 2-MByte or 4-MByte pages. This paging method can be used to map up to 2048 pages (4 page-directory-pointer-table entries times 512 page-directory entries) into a 4-GByte linear address space. The 2-MByte or 4-MByte page size is selected by setting the PSE flag in control register CR4 and setting the page size (PS) flag in a page-directory entry (refer to Figure 3-14). With these flags set, the linear address is divided into three sections: • • • Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to an entry in the page-directory-pointer table. The selected entry provides the base physical address of a page directory. Page-directory entry—Bits 21 through 29 provide an offset to an entry in the page directory. The selected entry provides the base physical address of a 2-MByte or 4-MByte page. Page offset—Bits 0 through 20 provides an offset to a physical address in the page. 3.8.3. Accessing the Full Extended Physical Address Space With the Extended Page-Table Structure The page-table structure described in the previous two sections allows up to 4 GBytes of the 64-GByte extended physical address space to be addressed at one time. Additional 4-GByte sections of physical memory can be addressed in either of two way: • • Change the pointer in register CR3 to point to another page-directory-pointer table, which in turn points to another set of page directories and page tables. Change entries in the page-directory-pointer table to point to other page directories, which in turn point to other sets of page tables. 3-32 PROTECTED-MODE MEMORY MANAGEMENT Directory Pointer Linear Address 31 30 29 21 20 Offset Directory 21 9 Page Directory 0 2 or 4-MByte Pages Physical Address Page-DirectoryPointer Table 2 Directory Entry Dir. Pointer Entry 32* CR3 (PDBR) *32 bits aligned onto a 32-byte boundary 4 PDPTE ∗ 512 PDE = 2048 Pages Figure 3-19. Linear Address Translation With Extended Physical Addressing Enabled (2-MByte or 4-MByte Pages) 3.8.4. Page-Directory and Page-Table Entries With Extended Addressing Enabled Figure 3-20 shows the format for the page-directory-pointer-table, page-directory, and page-table entries when 4-KByte pages and 36-bit extended physical addresses are being used. Figure 3-21 shows the format for the page-directory-pointer-table and page-directory entries when 2-MByte or 4-MByte pages and 36-bit extended physical addresses are being used. The functions of the flags in these entries are the same as described in Section 3.6.4., “Page-Directory and Page-Table Entries”. The major differences in these entries are as follows: • • • • A page-directory-pointer-table entry is added. The size of the entries are increased from 32 bits to 64 bits. The maximum number of entries in a page directory or page table is 512. The base physical address field in each entry is extended to 24 bits. 3-33 PROTECTED-MODE MEMORY MANAGEMENT Page-Directory-Pointer-Table Entry 63 36 35 32 Rese...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online